Supersedes October 1996 version, DS3707 - 4.2

DS3707 - 5.3 October 1997

PDSP16116

16 X 16 Bit Complex Multiplier

FEATURES

APPLICATIONS

ORDERING INFORMATION

PDSP16116 MC GGDR

10MHz MIL-883 screened

PDSP16116A B0 AC

20MHz Industrial

PDSP16116A A0 AC

20MHz Military

PDSP16116A B0 GG

20MHz Industrial

PDSP16116A MC GGDR 20MHz MIL-883 screened

PDSP16116B B0 AC

25MHz Industrial

PDSP16116D B0 GG

31·5MHz Industrial

ASSOCIATED PRODUCTS

PDSP16318/A Complex Accumulator

PDSP16112/A (16116)3(12112) Complex Multiplier

PDSP16330/A Pythagoras Processor

PDSP1601/A

ALU and Barrel Shifter

PDSP16350

Precision Digital Modulator

PDSP16256

Programmable FIR Filter

PDSP16510

Single Chip FFT Processor

Fig. 1 Simplified block diagram

PR15:0

ADD/SUB

REG

MULT

REG

REG

MULT

REG

REG

MULT

REG

REG

MULT

REG

ADD/SUB

SHIFT

REG

SHIFT

REG

PI15:0

XR15:0

XI15:0

YR15:0

YI15:0

The PDSP16116 contains four 16316 array multipliers, two

32-bit adder/subtractors and all the control logic required to sup-

port Block Floating Point Arithmetic as used in FFT applications.

The PDSP16116A variant will multiply two complex (16116)

bit words every 50ns and can be configured to output the com-

plete complex (32132) bit result within a single cycle. The data

format is fractional two’s complement.

In combination with a PDSP16318A, the PDSP16116A forms

a two-chip 20MHz complex multiplier accumulator with 20-bit

accumulator registers and output shifters. The PDSP16116A in

combination with two PDSP16318As and two PDSP1601As

forms a complete 20MHz Radix 2 DIT FFT butterfly solution

which fully supports block floating point arithmetic. The

PDSP16116 has an extremely high throughput that is suited to

recursive algorithms as all calculations are performed with a

single pipeline delay (two cycle fall-through).