PDSP16510

21

ABSOLUTE MAXIMUM RATINGS [See Notes]

Supply voltage Vcc

-0.5V to 7.0V

Input voltage V

IN

-0.5V to Vcc + 0.5V

Output voltage V

OUT

-0.5V to Vcc + 0.5V

Clamp diode current per pin I

18mA

Static discharge voltage (HMB)

500V

Storage temperature T

S

-65°C to 150°C

Junction Temperature, Commercial

100°C

Junction temperature, Industrial

115°C

Junction Temperature, Military

155°C

Package power dissipation

5000mW

Delay from output

high to output

high impedance

Test

Waveform - measurement level

Delay from output

low to output

high impedance

H

V

0.5V

V

0.5V

L

1.5V

0.5V

1.5V

0.5V

Delay from output

high impedance to

output low

Delay from output

high impedance to

output high

V

- Voltage reached when output driven high

V

- Voltage reached when output driven low

H

L

Units

V

V

V

V

µA

pF

µA

mA

Symbol

V

OH

V

OL

V

IH

V

IL

I

IN

C

IN

I

OZ

I

SC

Min.

2.4

-

2.0

-

-10

-50

10

Characteristic

Output high voltage

Output low voltage

Input high voltage

Input low voltage

Input leakage current

Input capacitance

Output leakage current

Output S/C current

Max.

-

0.4

-

0.8

+10

+50

300

Value

Typ.

10

NOTES ON MAXIMUM RATINGS

1. Exceeding these ratings may cause permanent damage.

Functional operation under these conditions is not implied.

2. Maximum dissipation or 1 second should not be exceeded,

only one output to be tested at any one time.

3. Exposure to absolute maximum ratings for extended

periods may affect device reliablity.

4. Current is defined as positive into the device.

ELECTRICAL CHARACTERISTICS

Operating Conditions (unless otherwise state)

PDSP16510A C0Tamb =

0 C to + 70°C.

Vcc = 5.0v ± 5%

PDSP16510A B0Tamb = -40 C to + 85°C.

Vcc = 5.0v ± 10%

PDSP16510A A0Tamb = -55 C to +125°C. Vcc = 5.0v ± 10%

Characteristic

Symbol

Min

Max

Conditions

Clock Frequency ( MHz )

Ø

DC

40

Max Ø high time is 1msec

Clock High Period ( ns )

T

CH

13

Clock Low Period ( ns )

T

CL

10

Max DOS, DIS Frequency

Ø

D

FØ

Less than 1024 points or Mult Dev Mode 1

Note F =

4

6 + 0.001ØT

CL

Max DIS Frequency

Ø

D

Ø

1024 points or Mult Dev Modes 2 and 3

Max DOS Frequency

Ø

D

Ø

Notes

I

I

SCLK, DIS, DOS, DEN need 3V

DEN needs 0.7V max

GND < V

GND < V

V

SWITCHING CHARACTERISTICS

SCLK to DIS/DOS RELATIONSHIP

Both DIS and DOS must be synchronous to SCLK. Ideally they should both be produced from SCLK, in which case the

SCLK rising edge would either be first or coincident with the DIS and DOS rising edges.

In any event, the rising edge of SCLK must not fall between 2ns and 10ns after the rising edge of either DIS or DOS