4

SP5055

A0

0

1

0

1

0

Voltage input to P6

Bits 3, 4 and 5 (I2,I1,I0) show the status of the I/O Ports P7,

P5 and P4 respectively. A logic 0 indicates a low level and a logic

1 a high level. If the ports are to be used as inputs they should

be programmed to a high impedance state (logic 1). These

inputs will then respond to data complying with TTL type voltage

levels. Bits 6, 7 and 8 (A2,A1,A0) combine to give the output of

the 5 level ADC.

The 5 level ADC can be used to feed AFC information to

the microprocessor from the IF section of the receiver, as

illustrated in the typical application circuit.

APPLICATION

A typical Application is shown in Fig. 4. All input/output

interface circuits are shown in Fig. 6.

Table 1 Write data format (MSB transmitted first)

Byte 1

Byte 2

Byte 3

Byte 4

Byte 5

Address

Programmable divider

Programmable divider

Charge pump and test bits

I/O port control bits

1

CP

P6

0

T1

P5

0

T0

P4

0

1

P3

MA0

1

X

MA1

1

X

A

A

A

A

A

MSB

1

0

1

P7

LSB

0

OS

P0

Table 2 Read data format (MSB is transmitted first)

Byte 1

Byte 2

Address

Status byte

1

FL

0

I2

0

I1

0

I0

MA0

A1

MA1

A2

A

A

1

POR

1

A0

A

: Acknowledge bit

MA1, MA0

: Variable address bits (see Table 4)

CP

: Charge Pump current select

T1

: Test mode selection

T0

: Charge pump disable

OS

: Varactor drive Output disable Switch

P7, P6, P5, P4,

: Control output states

P3, P0

POR

: Power On Reset indicator

FL

: Phase lock detect flag

I2, I1, I0

: Digital information from Ports P7, P5 and P4, respectively

A2, A1, A0

: 5 Level ADC data from P6 (see Table 3)

X

: Don't care

Table 4 Address selection

MA0

0

1

0

1

MA1

0

0

1

1

Voltage input to P3

Always valid

A1

0

1

1

0

0

A2

1

0

0

0

0

Table 3 ADC levels

Fig. 3 Data formats