5

SP5659

The POR is reset to 0 when the read sequence is terminated

programmed information is lost and the output ports are all set

to high impedance.

Bit 2 (FL) indicates whether the device is phase locked, a

logic ‘1’ is present if the device is locked, and a logic ‘0’ if the

device is unlocked.

Bits 6, 7 and 8 (A2, A1, A0) combine to give the output of

the ADC. The ADC can be used to feed AFC information to the

Additional Programmable Features

Prescaler enable

The 42 prescaler is enabled by setting bit PE in byte 4 to

a logic ‘1’. A logic ‘0’ disables the prescaler, directly passing

the RF input to the 17-bit counter. Bit PE is a static select only.

Charge pump current

The charge pump current can be programmed by bits C1 and

C0 in data byte 5, as defined in Fig. 3, Table 7.

Test mode

The test modes are invoked by setting bit RE to logic ‘0’ and

bit RTS to logic ‘1’ within the programming data and are selected

by bits TS2, TS1 and TS0 as shown in Fig. 3, Table 6. When TS2,

TS1 and TS0 are received, the device retains previously P2, P1

and P0 data.

Reference comparison frequency output

COMP output (pin 3) by setting byte 5 bit RE to logic ‘1’ and bit

switched to the REF/COMP output by setting bit RE to logic ‘1’

and bit RTS to logic ‘1’. For RE set to logic ‘0’, the output is

disabled and set to a high state. RE and RTS default to logic ‘1’

Table 1 Write data format (MSB transmitted first)

Table 3 Read data format

1

POR

1

A0

Byte 1

Byte 2

Address

Status byte

1

FL

0

X

0

X

0

X

MA0

A1

MA1

A2

A

A

Address input voltage level

Open circuit

Table 4 ADC levels

MA0

0

1

0

1

MA1

0

0

1

1

Table 5 Address selection

Voltage on ADC input

A1

0

1

1

0

0

A2

1

0

0

0

0

A0

0

1

0

1

0

A

:

Acknowledge bit

MA1, MA0

:

Variable address bits (see Table 5)

:

Programmable division ratio control bits

PE

:

Prescaler enable

R3, R2, R1, R0

:

Reference division ratio select (see Table 1)

C1, C0

:

Charge pump current select (see Table 7)

RE

:

Reference oscillator output enable

RTS

:

REF/COMP select when RE = 1, Test mode enable when RE = 0 (see Table 6)

TS2, TS1, TS0

:

Test mode control bits (valid when RE = 0 and RTS = 1,see Table 6)

P0

:

Port P0 output state (always valid except when RE = 0 and RTS = 1 (see Table 6)

P3, P2, P1

:

Ports P2, P1 and P0 output states

POR

:

Power on reset indicator

FL

:

Phase lock flag

A2, A1, A0

:

ADC data (see Table 4)

X

:

Don’t care

Address

Programmable divider

Programmable divider

Control data

Control data

MA0

R1

P1/TS1

1

C0

0

RE

0

PE

RTS

0

R3

P3

MSB

1

0

1

C1

MA1

R2

P2/TS2

LSB

0

R0

P0/TS0

Byte 1

Byte 2

Byte 3

Byte 4

Byte 5

A

A

A

A

A

Fig. 3 Data formats

cont…