SP8402

The SP8402 is a very low phase noise divider which divides

by powers of two. The S0, S1, S2 data inputs select the division

used to reduce the phase noise considerably below that

produced by standard dividers. The data inputs are CMOS or

TTL compatible.

The SP8402 is packaged in a 28 pin plastic SO package to

be compatible with the SP8400 and SP8401 devices.

FEATURES

s Very low Phase Noise (Typically -155 to 160dBc/Hz at 1kHz

offset)

s Supply Voltage 5V

ABSOLUTE MAXIMUM RATINGS

Supply Voltage

6.5V

Output Current

20mA

Storage Temperature Range

-55

°C to +125°C

Maximum Clock Input Voltage

2.5V p-p

ORDERING INFORMATION

SP8402 KG MPES (Commercial Grade)

MP28

Fig.1 Pin connections - top view

DS3738 - 2.1 March 1994

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

N/C

N/C

N/C

GND

CLOCK INPUT

CLOCK INPUT

CLOCK INPUT

GND

N/C

S0

N/C

N/C

N/C

N/C

N/C

N/C

N/C

OUTPUT

OUTPUT

N/C

N/C

S2

S1

CLOCK INPUT

Fig.2 Typical single sideband phase noise measured at 768MHz

Frequency (Hz)

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

–140

–150

–160

–170

10

100

1k

10k

100k