SM5876AM datasheet(14/17 Pages) NPC

14 / 17 page

SM5876AM

NIPPON PRECISION CIRCUITS—14

Inﬁnity-Zero Detector (analog mute control) Output (MUTEO)

Also from immediately after a reset input on RSTN

until the initialization cycle ﬁnishes and the ﬁrst data

cycle occurs.

In cases 1 and 2, from when an inﬁnity-zero is

detected a period of 214

× (1/fs) ≈ 0.37 seconds takes

place before MUTEO goes HIGH.

In cases 3 and 4, from when the attenuation counter

value is 0 a period of 214

× (1/fs) ≈ 0.37 seconds

takes place before MUTEO goes HIGH.

The SM5876AM outputs an inﬁnity-zero detection

output signal under the following circumstances.

1. When an inﬁnity-zero occurs on both the left and

right channels.

2. When an inﬁnity-zero occurs in the input data for

the channel set by the output mode setting.

3. When the output mode setting is muting for both

the left and right channels.

4. When the attenuation counter for both the left and

right channels is 0 (

−∞).

Figure 2. MUTEO output timing

LRCI

RSTN

MUTEO

2 /fs

Signal

No Signal

Initialize

Audio Data Input (DI, BCKI, LRCI)

The digital audio data is input on DI in MSB-ﬁrst,

2s-complement, 16-bit serial format.

Serial data bits are read into the SIPO register (serial-

to-parallel converter register) on the rising edge of

the bit clock BCKI.

The arithmetic operation and output timing are inde-

pendent of the input timing. Accordingly, after a

reset, as long as the clock frequency ratio between

LRCI and the system clock XTI is maintained, phase

differences between LRCI, BCKI and the system

clock XTI do not affect the functional operation.

Also, any jitter present on the data input clock does

not appear as output pulse jitter.

The bit clock frequency on BCKI should be between

32fs and 64fs.

Operating Modes (MLEN, MDT, MCK)

The microcontroller data is used to control the fol-

lowing parameters.

Digital attenuator

Digital attenuation is controlled by attenuation data

input on MDT.

The attenuation operation is determined by a mathe-

matical operation of the internal 8-bit up/down

counter’s output data on the signal data. The 8-bit

up/down counter, when attenuation data is input on

MDT, can control the left and right channels either

independently or together (independent when the

MDT attenuation control ﬂag is LOW, and together

when HIGH).

The left-channel counter contents DATTL and the

right-channel counter contents DATTR control the

left-channel gain and right-channel gain, respec-

tively, using the following equations.

After

system

reset

initialization,

independent

left/right-channel attenuation mode with the maxi-

mum gain of 0 dB is the default.

Deemphasis ﬁlter (MDT DEM ﬂag)

The built-in digital deemphasis ﬁlter is designed to

operate at 44.1 kHz. Deemphasis is ON when the

DEM ﬂag is HIGH, and OFF when the DEM ﬂag is

LOW. After reset, deemphasis OFF is the default.

Left-channel gain

DATTL

255

-------------------





log

[dB]

Right-channel gain

DATTR

255

--------------------





log

[dB]

SM5876AM Datasheet(PDF) 14 Page - Nippon Precision Circuits Inc

SM5876AM Datasheet(HTML) 14 Page - Nippon Precision Circuits Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

Datasheet Download

Link URL