SP8853BHC datasheet(6/14 Pages) MITEL

6 / 14 page

SP8853A/B

An F1 or F2 update cycle will consist of a byte containing

24 bits whereas the reference byte will contain 18 bits. The

device requires 3 bytes, each with a chip select sequence,

totalling 66 bits to fully program.

When the dual modulus

A counter is set to 48/9, the data

required to set the counter is reduced by one bit, leaving an

unused bit in the 22-bit F1/F2 buffer. This bit must always be

set to zero when the 48/9 mode is required. Various

programming sequences are shown in Fig. 7.

The data entry and storage registers are always powered

up, making it possible to enter data when the device is in the

powered down state.

PD2

Result

FREF and FPD outputs off, charge pumps 1 and 2 on

FREF and FPD outputs on, charge pump 1 off, charge pump 2 on

FREF and FPD outputs off, charge pump 1 disabled by lock detect, charge pump 2 on

FREF and FPD outputs on, charge pump 1 disabled by lock detect, charge pump 2 on

Table 4

Fig. 6 Application diagrams

CONTROL

MICRO

432

SP8853

33p

39p

FREF

FPD

0·1

SL562

−

LOOP FILTER

VOLTAGE

CONTROLLED

OSCILLATOR

VCC

RPD

2·2k

Rb >

0·25

PD2 current

Fig. 6a Typical application

128

SP8853

VCC

TO LOOP

AMPLIFIER

Fig. 6c Use of lock detect circuit with PD1

Fig. 6b Connection

of external reference

EXTERNAL

REFERENCE

SOURCE

22k

470

TO VCO

VARICAP

SUPPLY

10k

LOOP

FILTER

FROM

CHARGE

PUMP

Fig. 6d Simple discrete amplifier

Ra > 23

0·25

PD2 current

VCC

SP8853BHC Datasheet(PDF) 6 Page - Mitel Networks Corporation

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