VP2614

2

PIN DESCRIPTION

SIG

TYPE

FUNCTION

LD

I

Line input data

LEN

I

When low, the line input data is valid.

LCLK

I

Line input strobe

LRED

O

When low, line data cannot be ac

cepted.

DBUS7:0

O

Data and control bus to the VP2615.

DMODE3:0

O

These outputs identify the data on

DBUS7:0.

PM2:0

O

Identifiers for the additional information

on DBUS7:0 .Not used by the VP2615.

DCLK

O

Continuous O/P strobe for the DBUS7:0

bus which is derived from SCLK.

SCLK

I

System clock. Must be 27 MHz for 30 Hz

frame rates.

HD7:0

I/O

Bi-directional data bus.

HA3:0

I

Four system controller address bits.

WR

I

An active low write strobe from the

system controller.

RD

I

An active low read strobe from the

system controller.

CEN

I

An active low chip select from the sys

tem controller.

ERR

O

An active low output which Indicates

framing and decoding errors.

EVT

O

An active low output which Indicates

that new picture status data is available.

B7:0

I/O

Bi-directional data bus to the receive

buffer.

A14:0

O

Address bus to the receive buffer.

WS

O

An active low write strobe for the receive

buffer.

BCS

O

An active low select for the receive

buffer.

BEN

O

An active low output enable for the

buffer.

TCK

I

JTAG test clock

TMS

I

JTAG mode select

TDI

I

JTAG I/P data

TDO

O

JTAG O/P data

TRST

I

JTAG reset

TOE

I

When low all outputs are high imped-

ance

RES

I

An active low power on reset

OPERATION OF THE MAJOR BLOCKS

FRAME ALIGNMENT

The H.261 continuous bitstream is split into frames of 512

bits the first bit in each frame being part of an 8 bit frame

alignment pattern. Only the sequence in the pattern is impor-

tant and detection can start from any bit. To avoid false

detection within the actual data, this pattern must be repeated

at least three times before " frame lock " can be considered to

have been achieved.

The detection of frame lock thus requires data from 24

consecutive 512 bit frames, and a section of the Received

Data Buffer is reserved for this purpose. This external RAM is

supported by a small internal buffer which allows eight con-

secutive bits ( obtained from reading a byte ) to be simultane-

ously checked for alignment with the corresponding bits in

seven other bytes spaced apart by complete frames. The

search for alignment over 512 bits takes less than 250

microseconds with a 27 MHz clock, this being less than the

time taken to receive 512 bits at the maximum rate of 2Mb/

second. Thus the buffer area for frame lock does not overflow.

Once frame lock has been achieved it is continually

monitored using the appropriate bit in each frame. If a mis-

match occurs then the next four frame alignment bits will be

checked for errors. If any one of these four bits is also in error

then loss of frame alignment is declared by setting a Status

Register Bit, and a search for a new alignment position will

commence. If none are in error then a random bit error is

assumed and no further action is taken.

The check done on loss of alignment is a compromise

between falsely believing that alignment has been lost and not

detecting that frame alignment has been lost. The probability

of two random bit errors in the five frames used in the check

is dependent on the bit rate and also the error rate. With a high

error rate of 1:100000, and a bit rate of 2Mb/sec, false

detection is possible once per week. The probability of detect-

ing a change in the frame alignment ( caused by switching in

a new bitstream ) is 46.9% in the first five frames, but this rises

to 97.4% after 12 frames have been processed.

Control Bits allow H261 framing to be either identified or

ignored. In the latter case Frame Lock will always be indicated

and data is still buffered and processed. The datastream is

then expected to contain pure data and a search will be made

to find picture start codes. When framing is enabled the 18

parity bits are extracted from the data, but single bits in error

can still go un-detected in some circumstances.

NOTE:

"Barred" active low signals do not appear with a bar in the

main body of the text.