LMV612 datasheet(13/31 Pages) TI

13 / 31 page

LMV611, LMV612, LMV614

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SNOSC69B – APRIL 2012 – REVISED MARCH 2013

APPLICATION NOTE

INPUT AND OUTPUT STAGE

The rail-to-rail input stage of this family provides more flexibility for the designer. The LMV611/LMV612/LMV614

use a complimentary PNP and NPN input stage in which the PNP stage senses common mode voltage near V−

and the NPN stage senses common mode voltage near V+. The transition from the PNP stage to NPN stage

occurs 1V below V+. Since both input stages have their own offset voltage, the offset of the amplifier becomes a

function of the input common mode voltage and has a crossover point at 1V below V+.

This VOS crossover point can create problems for both DC and AC coupled signals if proper care is not taken.

Large input signals that include the VOS crossover point will cause distortion in the output signal. One way to

avoid such distortion is to keep the signal away from the crossover. For example, in a unity gain buffer

configuration and with VS = 5V, a 5V peak-to-peak signal will contain input-crossover distortion while a 3V peak-

to-peak signal centered at 1.5V will not contain input-crossover distortion as it avoids the crossover point.

Another way to avoid large signal distortion is to use a gain of

−1 circuit which avoids any voltage excursions at

the input terminals of the amplifier. In that circuit, the common mode DC voltage can be set at a level away from

the VOS cross-over point. For small signals, this transition in VOS shows up as a VCM dependent spurious signal in

series with the input signal and can effectively degrade small signal parameters such as gain and common mode

rejection ratio. To resolve this problem, the small signal should be placed such that it avoids the VOS crossover

point. In addition to the rail-to-rail performance, the output stage can provide enough output current to drive 600

Ω

loads. Because of the high current capability, care should be taken not to exceed the 150°C maximum junction

temperature specification.

INPUT BIAS CURRENT CONSIDERATION

The LMV611/LMV612/LMV614 family has a complementary bipolar input stage. The typical input bias current (IB)

is 15nA. The input bias current can develop a significant offset voltage. This offset is primarily due to IB flowing

through the negative feedback resistor, RF. For example, if IB is 50nA and RF is 100kΩ, then an offset voltage of

5mV will develop (VOS = IB x RF). Using a compensation resistor (RC), as shown in Figure 31, cancels this effect.

But the input offset current (IOS) will still contribute to an offset voltage in the same manner.

Figure 31. Canceling the Offset Voltage due to Input Bias Current

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LMV612 Datasheet(PDF) 13 Page - Texas Instruments