54ABT273

Octal D-Type Flip-Flop

General Description

The ’ABT273 has eight edge-triggered D-type flip-flops with

individual D inputs and Q outputs. The common buffered

Clock (CP) and Master Reset (MR) inputs load and reset

(clear) all flip-flops simultaneously.

The register is fully edge-triggered. The state of each D in-

put, one setup time before the LOW-to-HIGH clock transi-

tion, is transferred to the corresponding flip-flop’s Q output.

All outputs will be forced LOW independently of Clock or

Data inputs by a LOW voltage level on the MR input. The de-

vice is useful for applications where the true output only is re-

quired and the Clock and Master Reset are common to all

storage elements.

Features

n Eight edge-triggered D flip-flops

n Buffered common clock

n Buffered, asynchronous Master Reset

n See ’ABT377 for clock enable version

n See ’ABT373 for transparent latch version

n Output sink capability of 48 mA, source capability of

24 mA

n Guaranteed latchup protection

n High impedance glitch free bus loading during entire

power up and power down cycle

n Non-destructive hot insertion capability

n Disable time less than enable time to avoid bus

contention

n Standard Microcircuit Drawing (SMD) 5962-9321701

Ordering Code

Military

Package

Package Description

Number

54ABT273J-QML

J20A

20-Lead Ceramic Dual-In-Line

54ABT273W-QML

W20A

20-Lead Cerpack

54ABT273E-QML

E20A

20-Lead Ceramic Leadless Chip Carrier, Type C

July 1998

© 1998 National Semiconductor Corporation

DS100205

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