Z87010 datasheet(19/22 Pages) ZILOG

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Z87010/Z87L10

Zilog

Audio Encoder/Decoders

DS96WRL0601

P R E L I M I N A R Y

2-19

Figure 13. CODEC Interface Control Register

D15

D14

D13

D12

D11

D10

SCLK Prescaler (up-counter)

EXT7-1

SCLK/FSYNC Ratio Prescaler (up-counter)

CODEC Mode

01 Reserved

10 Reserved

11 Reserved

FSYNC

0 External Source*

1 Internal Source

CODEC 0 Disable/Enable

0 = Disable*

1 = Enable

Note: The timer is an up-counter.

Example: EXT7-1 = #%x00D

OSC = 12.288 MHz, SCLK = 2.048 MHz, FSYNC = 8 kHz

EXT7-1 = #%x80F

OSC = 12.288 MHz, SCLK = 6.144 MHz, FSYNC = 48 kHz

EXT7-1 = #%xFFx

No interrupt

EXT7-1 = #%x000

Max interrupt period (667

µs for OSC = 12.288 MHz)

* Default

Figure 14. Wait/State/CODEC Interface Control Register

D15

D14

D13

D12

D11

D10

EXT7-2

Wait State EXT0

Wait State EXT1

Wait State EXT2

Wait State EXT3

Wait State EXT4

Wait State EXT5

Wait State EXT6

SCLK

External Source*

Internal Source

CODEC 1 Disable/Enable

0 = Disable*

1 = Enable

nws - no wait states

ws - one wait states

00 no wait states (nws)

01 read (nws), write (ws)

10 read (ws), write (nws)

11 read (ws), write (ws)

*Default

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