Z86K14 datasheet(18/24 Pages) ZILOG

18 / 24 page

Z86K13/K14/K15/K16/K17/K18

CMOS Z8® 8-Bit MCU Keyboard Controllers

Zilog

P R E L I M I N A R Y

DS97KEY0204

PIN FUNCTIONS (Continued)

Power-On-Reset (POR). A timer circuit is triggered by the

system oscillator and is used for the Power-On Reset

(POR) timer function. The POR time allows V

CC and the os-

cillator circuit to stabilize before instruction execution be-

gins. POR period is defined as:

The POR timer circuit is a one-shot timer triggered by one

of two conditions:

Power fail to Power OK status

Stop-Mode Recovery

The POR time is a nominal 147 ms

±10%. At 4 MHz the

POR timer is bypassed after Stop-Mode Recovery.

HALT. HALT turns off the internal CPU clock, but not the

RC oscillator. The counter/timer and external interrupts

IRQ0, IRQ1, IRQ2, and IRQ3 remain active. The Z86K15

is recovered by interrupts, either externally or internally

(Figure 19).

STOP. This instruction turns off the internal clock and os-

cillator. It reduces the standby current to less than 10

µA.

The STOP Mode is terminated by a reset only or external

reset. This causes the processor to restart the application

program at address 000C (HEX) or the active external in-

terrupt vector. In order to enter STOP (or HALT) Mode, it

is necessary to first flush the instruction pipeline to avoid

suspending execution in mid-instruction. To do this, the

user must execute a NOP (Opcode=FFH) immediately be-

fore the appropriate sleep instruction, such as:

The Bit 6 of IRQ Registers are flags for STOP Mode Re-

covery (Figure 20).

Cold or Warm Start (D6). This bit is set upon entering

STOP Mode. A 0 (cold) indicates that the device is awak-

ened by a POR/WDT RESET. A 1 (warm) indicates that

the device is awakened by a SMR source. This bit is reset

when read.

Negative transition on any of the designated row input pins

or host data line will recover Z86KXX from STOP Mode.

POR (ms) =

589824

(Hz)

NOP

; clear the pipeline

STOP

; enter STOP Mode

NOP

; clear the pipeline

HALT

; enter HALT Mode

Figure 19. IRQ Register

R250 IRQ

IRQ0 = P32 Input

IRQ1 = P33 Input

IRQ2 = P31 Input

IRQ3 = P30 Input

IRQ4 = TO

WDT during HALT

0 OFF *

1 ON

Stop Flag

0 POR/WDT*

1 Stop Recovery

* On RESET

WDT Hot Bit (Read Only)

0 POR*

1 WDT Timeout

Figure 20. Stop-Mode Recovery Source

To Internal

RESET

P20-P26,

P30-P33

Z86K14 Datasheet(PDF) 18 Page - Zilog, Inc.

Z86K14 Datasheet(HTML) 18 Page - Zilog, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL