Z90102 datasheet(2/36 Pages) ZILOG

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Z90102/90103/90104

40-Pin Low-Cost Digital Television Controller

Zilog

DS97TEL1902

GENERAL DESCRIPTION (Continued)

together with the Z86C27 and Z86127 to provide support

for mid range and low end TV applications.

Zilog’s DTC offers fast execution, efficient use of memory,

sophisticated interrupts, input/output bit manipulation ca-

pabilities, and easy hardware/software system expansion

along with low cost and low power consumption. The de-

vice provides an ideal performance and reliability solution

for consumer and industrial television applications.

The Z90102/3/4 architecture is characterized by utilizing

Zilog’s advanced Superintegration™ design methodology.

The device has an 8-bit internal data path controlled by a

Z8 microcontroller and On Screen Display (OSD) logic cir-

cuits and Pulse Width Modulators (PWM). On-chip periph-

erals include two register mapped I/O ports (Ports 2 and

3), interrupt control logic (one software, two external and

three internal interrupts) and a standby mode recovery in-

put port (Port 3, P30).

The OSD control circuits support 6 rows x 20 columns of

characters. The character color is specified by row. One of

the six rows is assigned to show two kinds of colors for bar

type displays such as volume control. The OSD is capable

of displaying either low resolution (5 x 7 dot pattern) or high

resolution (11 x 15 dot pattern) characters.

A 14-bit PWM port provides enough voltage resolution for

a voltage synthesizer tuning system. Three 6-bit PWM

ports are used for controlling audio signal levels. Three 8-

bit PWM ports used to vary picture levels.

For DTC applications demanding powerful I/O capabili-

ties, the Z90102/3/4 fulfills this with 24 I/O pins dedicated

to input and output. These lines are grouped into three

ports, and are configurable under software control to pro-

vide timing, status signals, parallel I/O and an address/da-

ta bus for interfacing to external memory.

There are three basic address spaces available to support

this wide range of configurations: Program Memory, Video

RAM, and Register File. The Register File is composed of

236 bytes of general-purpose registers, two I/O Port regis-

ters, 15 control and status registers and three reserved

registers.

To unburden the program from coping with the real-time

problems such as counting/timing and data communica-

tion, the DTC offers two on-chip counter/timers with a large

number of user selectable modes (Figure 1).

Notes: All signals with a preceding front slash, "/", are ac-

tive Low. For example, B//W (WORD is active Low); /B/W

(BYTE is active Low, only).

Power connections follow conventional descriptions be-

low:

Connection

Circuit

Device

Power

VCC

VDD

Ground

GND

VSS

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