4

PRELIMINARY

Z89331

CP95TEL1400

PIN DESCRIPTIONS

Z89331

Pin

Z89331

Configuration

Name

Function

42-Pin SDIP

Direction

Reset

V

CC

+5 V

34

PWR

PWR

GND

0 V

13,30

PWR

PWR

IRIN

Infrared Remote Capture Input

36

I

I

4-Bit Analog to Digital Converter

–,9,10,11,12,2,8

AI

I

PWM9

14-Bit Pulse Width Modulator

1,2

OD

O

Output

8-Bit Pulse Width Modulator

–,–,–,3,4

OD

OD

Output

5,6,7

Bit Programmable

21,–,–,–,–,–,

B

I

Input/Output Ports

38,37,35,–,–,

15,8,40,39,11

Bit Programmable

–,16,12,20,

B

I

Input/Output Ports

19,18,17,42,

41,14

4 1

BOD

4 2

BOD

I

3 9

BOD

I

4 0

BOD

I

XTAL1

Crystal Oscillator Input

3 1

AI

AI

XTAL2

Crystal Oscillator Output

3 2

AO

AO

LPF

Loop Filter

2 9

AB

AB

HSYNC

H_Sync

2 6

B

I

VSYNC

V_Sync

2 7

B

I

/RESET

Device Reset

3 3

I

I

V[3:1]

OSD Video Output

22,23,24

O

O

(Typically Drive B, G, and R Outputs)

Blank

OSD Blank Output

2 5

O

O

OSD Half Blank Output

2 1

O

I

RGB Digital

R[1:0],G[1:0], and B[1:0]

37,14,17,

O

I

Outputs of the RGB Matrix

16,19,18

Internal Processor SCLK

2 0

O

I

e) Port19 is not available on the 42-pin DIP version.

f)

SCL I/O pin is shared with Port01 or Port11.

g) SCD I/O pin is shared with Port02 or Port12.

h) Half Blank output is a function shared with Port0F.

i)

Digital RGB outputs and the internal SCLK are shared with Port1[5:0].

k)

Internal processor SCLK is shared with Port16.

Notes:

a) ADC1 input is shared with Port 17, ADC2 input Pin is shared with

Port 00. ADC3 input pin is shared with Port 05 and ADC4 input pin

is shared with Port 04.

b) ADC0 and ADC5 have a clamp circuit that facilitates Composite

video input.

c) PWM[8,7] is not available on the 42-pin DIP version.

d) Port0[F:A] is not available on the 42-pin DIP version.