ATmega16 datasheet(274/315 Pages) ATMEL

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274

ATmega16(L)

2466E–AVR–10/02

PROG_COMMANDS ($5)

The AVR specific public JTAG instruction for entering programming commands via the

JTAG port. The 15-bit Programming Command Register is selected as Data Register.

The active states are the following:

•

Capture-DR: The result of the previous command is loaded into the Data Register.

•

Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of the

previous command and shifting in the new command.

•

Update-DR: The programming command is applied to the Flash inputs

•

Run-Test/Idle: One clock cycle is generated, executing the applied command (not

always required, see Table 116 below).

PROG_PAGELOAD ($6)

The AVR specific public JTAG instruction to directly load the Flash data page via the

JTAG port. The 1024 bit Virtual Flash Page Load Register is selected as Data Register.

This is a virtual scan chain with length equal to the number of bits in one Flash page.

Internally the Shift Register is 8-bit. Unlike most JTAG instructions, the Update-DR state

is not used to transfer data from the Shift Register. The data are automatically trans-

ferred to the Flash page buffer byte by byte in the Shift-DR state by an internal state

machine. This is the only active state:

•

Shift-DR: Flash page data are shifted in from TDI by the TCK input, and

automatically loaded into the Flash page one byte at a time.

PROG_PAGEREAD ($7)

The AVR specific public JTAG instruction to read one full Flash data page via the JTAG

port. The 1032 bit Virtual Flash Page Read Register is selected as Data Register. This is

a virtual scan chain with length equal to the number of bits in one Flash page plus 8.

Internally the Shift Register is 8-bit. Unlike most JTAG instructions, the Capture-DR

state is not used to transfer data to the Shift Register. The data are automatically trans-

ferred from the Flash page buffer byte by byte in the Shift-DR state by an internal state

machine. This is the only active state:

•

Shift-DR: Flash data are automatically read one byte at a time and shifted out on

TDO by the TCK input. The TDI input is ignored.

Note:

The JTAG instructions PROG_PAGELOAD and PROG_PAGEREAD can only be used if

the AVR devce is the first decive in JTAG scan chain. If the AVR cannot be the first

device in the scan chain, the byte-wise programming algorithm must be used.

Data Registers

The Data Registers are selected by the JTAG instruction registers described in section

“Programming Specific JTAG Instructions” on page 272. The data registers relevant for

programming operations are:

•

Reset Register

•

Programming Enable Register

•

Programming Command Register

•

Virtual Flash Page Load Register

•

Virtual Flash Page Read Register

Reset Register

The Reset Register is a Test Data Register used to reset the part during programming. It

is required to reset the part before entering programming mode.

A high value in the Reset Register corresponds to pulling the external Reset low. The

part is reset as long as there is a high value present in the Reset Register. Depending

on the Fuse settings for the clock options, the part will remain reset for a Reset Time-out

Period (refer to “Clock Sources” on page 23) after releasing the Reset Register. The

output from this Data Register is not latched, so the reset will take place immediately, as

shown in Figure 115 on page 224.

ATMEGA16 Datasheet(PDF) 274 Page - ATMEL Corporation

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