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ATMEGA16 Datasheet(PDF) 288 Page - ATMEL Corporation

Part # ATMEGA16
Description  8-bit AVR Microcontroller with 16K Bytes In-System Programmable Flash
PDF  315 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

ATMEGA16 Datasheet(HTML) 288 Page - ATMEL Corporation

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ATmega16(L)
2466E–AVR–10/02
Two-wire Serial Interface Characteristics
Table 119 describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega16 Two-wire Serial
Interface meets or exceeds these requirements under the noted conditions.
Timing symbols refer to Figure 145.
Notes:
1. In ATmega16, this parameter is characterized and not 100% tested.
2. Required only for f
SCL > 100 kHz.
3. C
b = capacitance of one bus line in pF.
4. f
CK = CPU clock frequency
Table 119. Two-wire Serial Bus Requirements
Symbol
Parameter
Condition
Min
Max
Units
VIL
Input Low-voltage
-0.5
0.3 VCC
V
V
IH
Input High-voltage
0.7 V
CC
V
CC + 0.5
V
V
hys
(1)
Hysteresis of Schmitt Trigger Inputs
0.05 V
CC
(2)
–V
VOL
(1)
Output Low-voltage
3 mA sink current
0
0.4
V
t
r
(1)
Rise Time for both SDA and SCL
20 + 0.1C
b
(3)(2)
300
ns
t
of
(1)
Output Fall Time from V
IHmin to VILmax
10 pF < C
b < 400 pF
(3)
20 + 0.1C
b
(3)(2)
250
ns
tSP
(1)
Spikes Suppressed by Input Filter
0
50
(2)
ns
I
i
Input Current each I/O Pin
0.1V
CC < Vi < 0.9VCC
-10
10
µA
C
i
(1)
Capacitance for each I/O Pin
–
10
pF
fSCL
SCL Clock Frequency
fCK
(4) > max(16f
SCL, 250kHz)
(5)
0400
kHz
Rp
Value of Pull-up resistor
f
SCL ≤ 100 kHz
f
SCL > 100 kHz
tHD;STA
Hold Time (repeated) START Condition
f
SCL ≤ 100 kHz
4.0
–
µs
f
SCL > 100 kHz
0.6
–
µs
t
LOW
Low Period of the SCL Clock
fSCL ≤ 100 kHz
(6)
4.7
–
µs
f
SCL > 100 kHz
(7)
1.3
–
µs
t
HIGH
High period of the SCL clock
f
SCL ≤ 100 kHz
4.0
–
µs
fSCL > 100 kHz
0.6
–
µs
tSU;STA
Set-up time for a repeated START condition
f
SCL ≤ 100 kHz
4.7
–
µs
f
SCL > 100 kHz
0.6
–
µs
t
HD;DAT
Data hold time
fSCL ≤ 100 kHz
0
3.45
µs
f
SCL > 100 kHz
0
0.9
µs
t
SU;DAT
Data setup time
f
SCL ≤ 100 kHz
250
–
ns
fSCL > 100 kHz
100
–
ns
tSU;STO
Setup time for STOP condition
f
SCL ≤ 100 kHz
4.0
–
µs
f
SCL > 100 kHz
0.6
–
µs
t
BUF
Bus free time between a STOP and START
condition
fSCL ≤ 100 kHz
4.7
–
µs
f
SCL > 100 kHz
1.3
–
µs
V
CC
0,4V
–
3mA
----------------------------
1000ns
C
b
-------------------
Ω
V
CC
0,4V
–
3mA
----------------------------
300ns
C
b
----------------
Ω



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