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ATMEGA16 Datasheet(PDF) 289 Page - ATMEL Corporation |
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ATMEGA16 Datasheet(HTML) 289 Page - ATMEL Corporation |
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289 / 315 page  289 ATmega16(L) 2466E–AVR–10/02 5. This requirement applies to all ATmega16 Two-wire Serial Interface operation. Other devices connected to the Two-wire Serial Bus need only obey the general fSCL requirement. 6. The actual low period generated by the ATmega16 Two-wire Serial Interface is (1/f SCL - 2/fCK), thus fCK must be greater than 6 MHz for the low time requirement to be strictly met at f SCL = 100 kHz. 7. The actual low period generated by the ATmega16 Two-wire Serial Interface is (1/f SCL - 2/fCK), thus the low time requirement will not be strictly met for fSCL > 308 kHz when f CK = 8 MHz. Still, ATmega16 devices connected to the bus may communicate at full speed (400 kHz) with other ATmega16 devices, as well as any other device with a proper tLOW acceptance margin. Figure 145. Two-wire Serial Bus Timing SPI Timing Characteristics See Figure 146 and Figure 147 for details. tSU;STA tLOW tHIGH tLOW tof tHD;STA tHD;DAT tSU;DAT tSU;STO tBUF SCL SDA tr Table 120. SPI Timing Parameters Description Mode Min Typ Max 1 SCK period Master See Table 58 ns 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master 3.6 4 Setup Master 10 5Hold Master 10 6 Out to SCK Master 0.5 • t SCK 7 SCK to out Master 10 8 SCK to out high Master 10 9SS low to out Slave 15 10 SCK period Slave 4 • tck 11 SCK high/low Slave 2 • tck 12 Rise/Fall time Slave 1.6 µs 13 Setup Slave 10 ns 14 Hold Slave 10 15 SCK to out Slave 15 16 SCK to SS high Slave 20 17 SS high to tri-state Slave 10 18 SS low to SCK Slave 2 • tck |
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