Functional Description

The ’AC191 is a synchronous up/down counter. The ’AC191

is organized as a 4-bit binary counter. It contains four

edge-triggered flip-flops with internal gating and steering

logic to provide individual preset, count-up and count-down

operations.

Each circuit has an asynchronous parallel load capability

permitting the counter to be preset to any desired number.

When the Parallel Load (PL) input is LOW, information

present on the Parallel Load inputs (P

the counter and appears on the Q outputs. This operation

overrides the counting functions, as indicated in the Mode

Select Table.

A HIGH signal on the CE input inhibits counting. When CE is

LOW, internal state changes are initiated synchronously by

the LOW-to-HIGH transition of the clock input. The direction

of counting is determined by the U/D input signal, as indi-

cated in the Mode Select Table. CE and U/D can be changed

with the clock in either state, provided only that the recom-

mended setup and hold times are observed.

Two types of outputs are provided as overflow/underflow in-

dicators. The terminal count (TC) output is normally LOW. It

goes HIGH when the circuits reach zero in the count down

mode or 15 in the count up mode. The TC output will then re-

main HIGH until a state change occurs, whether by counting

or presetting or until U/D is changed. The TC output should

not be used as a clock signal because it is subject to decod-

ing spikes.

The TC signal is also used internally to enable the Ripple

Clock (RC) output. The RC output is normally HIGH. When

CE is LOW and TC is HIGH, RC output wil go LOW when the

clock next goes LOW and will stay LOW until the clock goes

HIGH again. This feature simplifies the design of multistage

counters, as indicated in

Figure 1 and Figure 2.In Figure 1,

each RC output is used as the clock input for the next higher

stage. This configuration is particularly advantageous when

the clock source has a limited drive capability, since it drives

only the first stage. To prevent counting in all stages it is only

necessary to inhibit the first stage, since a HIGH signal on

CE inhibits the RC output pulse, as indicated in the RC Truth

Table. A disadvantage of this configuration, in some applica-

tions, is the timing skew between state changes in the first

and last stages. This represents the cumulative delay of the

clock as it ripples through the preceding stages.

A method of causing state changes to occur simultaneously

in all stages is shown in

Figure 2. All clock inputs are driven

in parallel and the RC outputs propagate the carry/borrow

signals in ripple fashion. In this configuration the LOW state

duration of the clock must be long enough to allow the

negative-going edge of the carry/borrow signal to ripple

through to the last stage before the clock goes HIGH. There

is no such restriction on the HIGH state duration of the clock,

since the RC output of any device goes HIGH shortly after its

CP input goes HIGH.

The configuration shown in

Figure 3 avoids ripple delays and

their associated restrictions. The CE input for a given stage

is formed by combining the TC signals from all the preceding

stages. Note that in order to inhibit counting an enable signal

must be included in each carry gate. The simple inhibit

scheme of

Figure 1 and Figure 2 doesn’t apply, because the

TC output of a given stage is not affected by its own CE.

Mode Select Table

Inputs

Mode

PL

CE

U/D

CP

HL

L

N

Count Up

HL

H

N

Count Down

L

X

X

X

Preset (Asyn.)

H

H

X

X

No Change (Hold)

RC Truth Table

Inputs

Outputs

PL

CE

CP

RC

HL

H

JJ

HH

X

X

H

H

XLX

H

L

XXX

H

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

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