54AC251F datasheet(2/10 Pages) NSC

2 / 10 page

Connection Diagrams

Functional Description

This device is a logical implementation of a single-pole,

8-position switch with the switch position controlled by the

state of three Select inputs, S

0,S1,S2.

Both true and

complementary outputs are provided. The Output Enable in-

put ( OE) is active LOW. When it is activated, the logic func-

tion provided at the output is:

Z = OE

•

0 • S0 • S1 • S2 +I1• S0 • S1 • S 2 +

2 • S0 • S 1 • S2 +I3 • S 0 • S1 • S2 +

4 • S0 • S1 • S2 +I5 • S 0 • S1 • S2 +

6 • S0 • S 1 • S2 +I7 • S0 • S1 • S2)

When the Output Enable is HIGH, both outputs are in the

high impedance (High Z) state. This feature allows multi-

plexer expansion by tying the outputs of up to 128 devices

together. When the outputs of the TRI-STATE devices are

tied together, all but one device must be in the high imped-

ance state to avoid high currents that would exceed the

maximum ratings. The Output Enable signals should be de-

signed to ensure there is no overlap in the active-LOW por-

tion of the enable voltages.

Truth Table

Inputs

Outputs

XXX

LLLL

LLL

LHLI

LHL

LHLH

HLI

HHHI

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Z = High Impedance

Pin Assignment

for DIP and Flatpak

DS100284-3

Pin Assignment

for LCC

DS100284-4

54AC251F Datasheet(PDF) 2 Page - National Semiconductor (TI)

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