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M37702S1AFP Datasheet(PDF) 31 Page - Mitsubishi Electric Semiconductor |
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M37702S1AFP Datasheet(HTML) 31 Page - Mitsubishi Electric Semiconductor |
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31 / 59 page  31 MITSUBISHI MICROCOMPUTERS M37702M2AXXXFP, M37702M2BXXXFP M37702S1AFP, M37702S1BFP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER ASYNCHRONOUS SERIAL COMMUNICATION Asynchronous serial communication can be performed using 7-, 8-, or 9-bit length data. The operation is the same for all data lengths. The following is the description for 8-bit asynchronous communication. With 8-bit asynchronous communication, the bit 0 of UARTi trans- mit/receive mode register is “1“, the bit 1 is “0”, and the bit 2 is “1”. Bit 3 is used to select an internal clock or an external clock. If bit 3 is “0”, an internal clock is selected and if bit 3 is “1”, then external clock is selected. If an internal clock is selected, the bit 0 (CS0) and bit 1 (CS1) of UARTi transmit/receive control register 0 are used to select the clock source. When an internal clock is selected for asynchronous serial communication, the CLKi pin can be used as a normal I/O pin. The selected internal or external clock is divided by (n +1), then by 16, and passed through a control circuit to create the UART trans- mission clock or UART receive clock. Therefore, the transmission speed can be changed by changing the contents n of the bit rate generator. If the selected clock is an internal clock fi or an external clock fEXT, Bit Rate = (fi or fEXT) / {(n + 1) ! 16} Bit 4 is the stop bit length selection bit to select 1 stop bit or 2 stop bits. The bit 5 is a selection bit of odd parity or even parity. In the odd parity mode, the parity bit is adjusted so that the sum of the 1’s in the data and parity bit is always odd. In the even parity mode, the parity bit is adjusted so that the sum of the 1’s in the data and parity bit is always even. Fig. 40 Transmit timing example when 8-bit asynchronous communication with parity and 1 stop bit is selected Fig. 41 Transmit timing example when 9-bit asynchronous communication with no parity and 2 stop bits is selected D6 D7 ST D1 D2 D3 D4 D5 P SP ST ST D0 D1 TEi (1 / f1 , or 1 / fEXT) ! (n + 1) ! 16 Transmission clock CTSi Write in transmission buffer register TIi TENDi TXDi TXEPTYi Transmission register ← Transmission buffer register Stopped because TEi = “0” Start bit Parity bit Stop bit D0 D6 D7 D1 D2 D3 D4 D5 P SP D0 TEi Transmission clock TIi TENDi TXDi TXEPTYi (1 / f1 or 1 / fEXT) ! (n + 1) ! 16 Write in transmission buffer register Transmission register ← Transmission buffer register Stopped because Start bit Stop Bit Stop Bit TEi = “0” D6 ST D1 D2 D3 D4 D5 D8 SP ST D0 D1 D0 D6 D7 D1 D2 D3 D4 D5 SP D0 D7 SP SP D8 ST D2 |
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