Connection Diagrams

Functional Description

The ’ACT323 contains eight edge-triggered D-type flip-flops

and the interstage logic necessary to perform synchronous

reset, shift left, shift right, parallel load and hold operations.

The type of operation is determined by S

in the Mode Select Table. All flip-flop outputs are brought out

through TRI-STATE buffers to separate I/O pins that also

serve as data inputs in the parallel load mode. Q

also brought out on other pins for expansion in serial shifting

of longer words.

A LOW signal on SR overrides the Select inputs and allows

the flip-flops to be reset by the next rising edge of CP. All

other state changes are also initiated by the LOW-to-HIGH

CP transition. Inputs can change when the clock is in either

state provided only that the recommended setup and hold

times, relative to the rising edge of CP, are observed.

A HIGH signal on either OE

buffers and puts the I/O pins in the high impedance state. In

this condition the shift, load, hold and reset operations can

still occur. The TRI-STATE buffers are also disabled by HIGH

signals on both S

operation.

Mode Select Table

Inputs

Response

SR

S

1

S

0

CP

LX

X

N

Synchronous Reset; Q

HH

H

N

Parallel Load; I/O

HL

H

N

Shift Right; DS

HH

L

N

Shift Left; DS

H

L

L

X

Hold

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Pin Assignment for

DIP and Flatpak

DS100328-2

Pin Assignment

for LCC

DS100328-3

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