Block Diagram

Functional Description

Data transfers into the diagnostic register occur on the

LOW-to-HIGH transition of DCLK. Mode and SDI determine

what data source will be loaded. The pipeline register is

loaded on the LOW-to-HIGH transition of PCLK. Mode se-

lects whether the data source is the data input or the diag-

nostic register output. Because of the independence of the

clock inputs, data can be shifted in the diagnostic register via

DCLK and loaded into the pipeline register from the data in-

put via PCLK simultaneously, as long as no setup or hold

times are violated. This simultaneous operation is legal.

Function Table

Inputs

Outputs

Operation

SDI

MODE

DCLK

PCLK

SDO

Diagnostic Reg.

Pipeline Reg.

X

L

N

X

S7

NA

Serial Shift; D

I

X

L

X

N

S7

NA

Normal Load Pipeline Register

LH

N

X

L

NA

Load Diagnostic Register from Y;

DI Disabled

X

H

X

N

SDI

NA

Load Pipeline Register from

Diagnostic Register

H

H

N

X

H

Hold

NA

Hold Diagnostic Register; DI

Enabled

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

N = LOW-to-HIGH Clock Transition

DS100251-5

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