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54ACTQ533D Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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54ACTQ533D Datasheet(HTML) 1 Page - National Semiconductor (TI) |
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1 / 8 page  54ACTQ533 Quiet Series Octal Transparent Latch with TRI-STATE® Outputs General Description The ACTQ533 consists of eight latches with TRI-STATE out- puts for bus organized system applications. The flip-flops ap- pear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing re- quirements is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus out- put is in the high impedance state. The ACTQ533 utilizes NSC Quiet Series technology to guar- antee quiet output switching and improve dynamic threshold performance. FACT Quiet Series™ features GTO™ output control and undershoot corrector in addition to a split ground bus for superior performance. Features n ICC and IOZ reduced by 50% n Guaranteed simultaneous switching noise level and dynamic threshold performance n Improved latch up immunity n Eight latches in a single package n TRI-STATE outputs drive bus lines or buffer memory address registers n Outputs source/sink 24 mA n Inverted version of the ACTQ373 n 4 kV minimum ESD immunity Logic Symbols Pin Names Description D 0–D7 Data Inputs LE Latch Enable Input OE Output Enable Input O 0–O7 TRI-STATE Latch Outputs GTO™ is a trademark of National Semiconductor Corporation. TRI-STATE® is a registered trademark of National Semiconductor Corporation. FACT® is a registered trademark of Fairchild Semiconductor Corporation. FACT Quiet Series™ is a trademark of Fairchild Semiconductor Corporation. DS100241-1 IEEE/IEC DS100241-2 August 1998 © 1998 National Semiconductor Corporation DS100241 www.national.com |
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