MEC1322 datasheet(315/456 Pages) MICROCHIP

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DS00001719D-page 315

MEC1322

• The DIRECTION bit is equal to the BIOEN bit when data is not being shifted out (i.e., SPI interface is idle).

• The hardware samples the BIOEN bit when it is shifting out the last bit of a byte to determine if the buffer needs to

be turned around for the next byte.

• The BIOEN bit is also sampled any time the value in the TX_DATA register is loaded into the shift register to be

transmitted.

If a TAR (Turn-around time) is required between transmitting and receiving bytes on the SPDOUT signal, software

should allow all the bytes to be transmitted before changing the buffer to an input and then load the TX_DATA register

to begin receiving bytes. If TAR greater than zero is required, software must wait for the transmission in one direction

to complete before writing the TX_DATA register to start sending/receiving in the opposite direction. This allows the SPI

block to operate the same as legacy Microchip SPI devices.

27.10.5

CONFIGURING THE SPI CLOCK GENERATOR

The SPI controller generates the SPI_CLK signal to the external SPI device. The frequency of the SPI_CLK signal is

determined by one of two clock sources and the Preload value of the clock generator down counter. The clock generator

toggles the SPI_CLK output every time the counter underflows, while data is being transmitted.

The clock source to the down counter is determined by Bit CLKSRC. Either the main system clock or the 2MHz clock

can be used to decrement the down counter in the clock generator logic.

The SPI_CLK frequency is determined by the following formula:

The REFERENCE_CLOCK frequency is selected by CLKSRC in the SPI Clock Control Register and PRELOAD is the

PRELOAD field of the SPI Clock Generator Register. The frequency can be either the 48 MHz Ring Oscillator clock or

a 2MHz clock. When the PRELOAD value is 0, the REFERENCE_CLOCK is always the 48 MHz Ring Oscillator clock

and the CLKSRC bit is ignored.

Sample SPI Clock frequencies are shown in the following table:

27.10.6

CONFIGURING SPI MODE

In practice, there are four modes of operation that define when data should be latched. These four modes are the com-

binations of the SPI_CLK polarity and phase.

The output of the clock generator may be inverted to create an active high or active low clock pulse. This is used to

determine the inactive state of the SPI_CLK signal and is used for determining the first edge for shifting the data. The

polarity is selected by CLKPOL in the SPI Clock Control Register.

Note:

When the SPI interface is in the idle state and data is not being transmitted, the SPI_CLK signal stops in

the inactive state as determined by the configuration bits.

TABLE 27-7:

SPI_CLK FREQUENCIES

Clock Source

PRELOAD

SPI_CLK Frequency

Don’t Care

48MHz

24MHz

48MHz

12MHz

(default)

48MHz

6MHz

48MHz

381KHz

2MHz

1MHz

2MHz

500KHz

2MHz

333KHz

2MHz

15.9KHz

SPI_CLK_FREQ=

--- REFERENCE_CLOCK

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