MEC1322 datasheet(318/456 Pages) MICROCHIP

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MEC1322

DS00001719D-page 318

 2014 - 2015 Microchip Technology Inc.

• After 8 SPI_CLK pulses from the first transmit byte (Command Byte transmitted):

- The first SPI cycle is complete, RXBF bit is asserted '1', and the SPINT interrupt is asserted, if enabled. The

data now contained in SPIRD - SPI RX_Data Register is invalid since the last cycle was initiated solely to

transmit command data to the slave. This particular slave device tri-states the SPDIN pin to the master while

it is accepting command data. This SPIRD data is ignored.

- Once the first SPI cycle is completed, the SPI master takes the pending data in the TX_DATA register

(EEPROM address A15-A8) and loads it into the TX shift register. Loading the shift register automatically

asserts the TXFE bit, begins shifting the dummy data value onto the SPDOUT pin, and drives the SPI_CLK

pin. Data on the SPDIN pin is also sampled on each clock. Note: The particular slave device ignores address

A15-A13.

• Once the TXFE bit is asserted the SPI Master is ready to receive its next byte. Before writing the next TX_DATA

value, software must clear the RXBF status bit by reading the SPIRD - SPI RX_Data Register.

• Next, EEPROM address A7-A0 is written to the TX_DATA register. The SPI master automatically clears the TXFE

bit, but does not begin shifting this data value onto the SPDOUT pin. This byte will remain in the TX_DATA register

until the TX shift register is empty.

• After 8 SPI_CLK pulses from the second transmit byte (Address Byte (MSB) transmitted):

- EEPROM address A15-A8 has been transmitted to the slave completing the second SPI cycle. Once again,

the RXBF bit is asserted '1' and the SPINT interrupt is asserted, if enabled. The data now contained in SPIRD

- SPI RX_Data Register is invalid since the last cycle was initiated solely to transmit address data to the

slave.

- Once the second SPI cycle is completed, the SPI master takes the pending data in the TX_DATA register

(EEPROM address A7-A0) and loads it into the TX shift register. Loading the shift register automatically

asserts the TXFE bit, begins shifting the dummy data value onto the SPDOUT pin, and drives the SPCLK pin.

Data on the SPDIN pin is also sampled on each clock.

• Once the TXFE bit is asserted the SPI Master is ready to receive its next byte. Before writing the next TX_DATA

value, software must clear the RXBF status bit by reading the SPIRD - SPI RX_Data Register.

• Next, a dummy byte is written to the TX_DATA register. The SPI master automatically clears the TXFE bit, but

does not begin shifting this data value onto the SPDOUT pin. This byte will remain in the TX_DATA register until

the TX shift register is empty.

• After 8 SPI_CLK pulses, the third SPI cycle is complete (Address Byte (LSB) transmitted):

- EEPROM address A7-A0 has been transmitted to the slave completing the third SPI cycle. Once again, the

RXBF bit is asserted '1' and the SPINT interrupt is asserted, if enabled. The data now contained in SPIRD -

SPI RX_Data Register is invalid since the last cycle was initiated solely to transmit address data to the slave.

- Once the third SPI cycle is completed, the SPI master takes the pending data in the TX_DATA register

(dummy byte) and loads it into the TX shift register. Loading the shift register automatically asserts the TXFE

bit, begins shifting the dummy data value onto the SPDOUT pin, and drives the SPCLK pin. Data on the

SPDIN pin is also sampled on each clock.

• Once the TXFE bit is asserted the SPI Master is ready to receive its next byte. Before writing the next TX_DATA

value, software must clear the RXBF status bit by reading the SPIRD - SPI RX_Data Register.

• If only one receive byte is required, the host would not write any more value to the TX_DATA register until this

transaction completes. If more than one byte of data is to be received, another dummy byte would be written to the

TX_DATA register (one dummy byte per receive byte is required). The SPI master automatically clears the TXFE

bit when the TX_DATA register is written, but does not begin shifting this data value onto the SPDOUT pin. This

byte will remain in the TX_DATA register until the TX shift register is empty.

• After 8 SPI_CLK pulses, the fourth SPI cycle is complete (First Data Byte received):

- The dummy byte has been transmitted to the slave completing the fourth SPI cycle. Once again, the RXBF bit

is asserted '1' and the SPINT interrupt is asserted, if enabled. Unlike the command and address phases, the

data now contained in SPIRD - SPI RX_Data Register is the 8-bit EEPROM data since the last cycle was ini-

tiated to receive data from the slave.

- Once the fourth SPI cycle is completed, the SPI master takes the pending data in the TX_DATA register (if

any) and loads it into the TX shift register. This process will be repeated until all the desired data is received.

• The host software will read and store the EEPROM data value in SPIRD - SPI RX_Data Register.

Note:

External pull-up or pull-down is required on the SPDIN pin if it is tri-stated by the slave device.

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