MEC1322 datasheet(321/456 Pages) MICROCHIP

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MEC1322

• BIOEN is asserted '1' to indicate that data will now be driven by the master.

• Next, a command byte is written to the TX_DATA register. This value is the first half of a 16 bit command to be

sent to temperature sensor peripheral. The SPI master automatically clears the TXFE bit, but does not begin shift-

ing the command data value onto the SPDOUT pin. This byte will remain in the TX_DATA register until the TX shift

sampled on each clock.

• After 8 SPI_CLK pulses from the second receive byte:

- The second SPI cycle is complete, RXBF bit is asserted '1', and the SPINT interrupt is asserted, if enabled.

The data now contained in SPIRD - SPI RX_Data Register is the second half of the 16 bit word containing the

temperature data.

- Once the first SPI cycle is completed, the SPI master takes the pending data in the TX_DATA register (com-

mand byte 1) and loads it into the TX shift register. Loading the shift register automatically asserts the TXFE

bit, begins shifting the dummy data value onto the SPDOUT pin, and drives the SPI_CLK pin. Data on the

SPDIN pin is also sampled on each clock.

• Once the TXFE bit is asserted the SPI Master is ready to receive its next byte. Before writing the next TX_DATA

value, software must clear the RXBF status bit by reading the SPIRD - SPI RX_Data Register.

• Next, the second command byte is written to the TX_DATA register. The SPI master automatically clears the

TXFE bit, but does not begin shifting the command data value onto the SPDOUT pin. This byte will remain in the

TX_DATA register until the TX shift register is empty.

• After 8 SPI_CLK pulses from the first transmit byte:

- The third SPI cycle is complete, RXBF bit is asserted '1', and the SPINT interrupt is asserted, if enabled. The

data now contained in SPIRD - SPI RX_Data Register is invalid, since this command was used to transmit the

first command byte to the SPI slave.

- Once the first SPI cycle is completed, the SPI master takes the pending data in the TX_DATA register (com-

mand byte 2) and loads it into the TX shift register. Loading the shift register automatically asserts the TXFE

bit, begins shifting the dummy data value onto the SPDOUT pin, and drives the SPI_CLK pin. Data on the

SPDIN pin is also sampled on each clock.

• Once the TXFE bit is asserted the SPI Master is ready to transmit or receive its next byte. Before writing the next

TX_DATA value, software must clear the RXBF status bit by reading the SPIRD - SPI RX_Data Register.

• Since no more data needs to be transmitted, the host software will wait for the RXBF status bit to be asserted indi-

cating the second command byte was transmitted successfully.

• CS# is de-asserted.

27.12 EC-Only Registers

The registers listed in the EC-Only Register Summary table are for a single instance of the General Purpose Serial

Peripheral Interface. The addresses of each register listed in this table are defined as a relative offset to the host “Base

Address” defined in the EC-Only Register Base Address Table.

The Base Address indicates where the first register can be accessed in a particular address space for a block instance.

TABLE 27-9:

EC-ONLY REGISTER BASE ADDRESS TABLE

Block Instance

Instance

Number

Host

Address Space

Base Address

General Purpose Serial

Peripheral Interface

(GP-SPI)

32-bit internal

address space

4000_9400h

32-bit internal

address space

4000_9480h

Note:

The Shared SPI controller is instance 0 and the Private SPI is instance 1 of the General Purpose Serial

Peripheral Interface (GP-SPI) block.

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