MEC1322 datasheet(325/456 Pages) MICROCHIP

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DS00001719D-page 325

MEC1322

27.12.6

SPI CLOCK CONTROL REGISTER

This register should not be changed during an active SPI transaction.

Offset

00h

Bits

Description

Type

Default

Reset

Event

31:5 Reserved

4 CLKSRC

Clock Source for the SPI Clock Generator. This bit should not be

changed during a SPI transaction. When the field PRELOAD in the

SPI Clock Generator Register is 0, this bit is ignored and the Clock

Source is always the main system clock (the equivalent of setting

this bit to ‘0’).

1=2MHz

0=48 MHz Ring Oscillator

R/W

VCC1_R

ESET

3 Reserved

2 CLKPOL

SPI Clock Polarity.

1=The SPI_CLK signal is high when the interface is idle and the first

clock edge is a falling edge

0=The SPI_CLK is low when the interface is idle and the first clock

edge is a rising edge

R/W

VCC1_R

ESET

1 RCLKPH

Receive Clock Phase, the SPI_CLK edge on which the master will

sample data. The receive clock phase is not affected by the SPI

Clock Polarity.

1=Valid data on SPDIN signal is expected after the first SPI_CLK

edge. This data is sampled on the second and following even

SPI_CLK edges (i.e., sample data on falling edge)

0=Valid data is expected on the SPDIN signal on the first SPI_CLK

edge. This data is sampled on the first and following odd SPI_-

CLK edges (i.e., sample data on rising edge)

R/W

VCC1_R

ESET

0 TCLKPH

Transmit Clock Phase, the SPCLK edge on which the master will

clock data out. The transmit clock phase is not affected by the SPI

Clock Polarity.

1=Valid data is clocked out on the first SPI_CLK edge on SPDOUT

signal. The slave device should sample this data on the second

and following even SPI_CLK edges (i.e., sample data on falling

edge)

0=Valid data is clocked out on the SPDOUT signal prior to the first

SPI_CLK edge. The slave device should sample this data on the

first and following odd SPI_CLK edges (i.e., sample data on ris-

ing edge)

R/W

VCC1_R

ESET

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