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MEC1322 Datasheet(PDF) 322 Page - Microchip Technology |
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MEC1322 Datasheet(HTML) 322 Page - Microchip Technology |
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322 / 456 page  MEC1322 DS00001719D-page 322 2014 - 2015 Microchip Technology Inc. 27.12.1 SPI ENABLE REGISTER 27.12.2 SPI CONTROL REGISTER TABLE 27-10: EC-ONLY REGISTER SUMMARY Offset Register Name 0h SPI Enable Register 4h SPI Control Register 8h SPI Status Register Ch SPI TX_Data Register 10h SPI RX_Data Register 14h SPI Clock Control Register 18h SPI Clock Generator Register Offset 00h Bits Description Type Default Reset Event 31:1 Reserved R - - 0 ENABLE 1=Enabled. The device is fully operational 0=Disabled. Clocks are gated to conserve power and the SPDOUT and SPI_CLK signals are set to their inactive state R/W 0h VCC1_R ESET Offset 00h Bits Description Type Default Reset Event 31:7 Reserved R - - 6CE SPI Chip Select Enable. 1= SPI_CS# output signal is asserted, i.e., driven to logic ‘0’ 0= SPI_CS# output signal is deasserted, i.e., driven to logic ‘1’ R/W 0h VCC1_R ESET 5 AUTO_READ Auto Read Enable. 1=A read of the SPI RX_DATA Register will clear both the RXBF sta- tus bit and the TXBE status bit 0=A read of the SPI RX_DATA Register will clear the RXBF status bit. The TXBE status bit will not be modified R/W 0h VCC1_R ESET 4 SOFT_RESET Soft Reset is a self-clearing bit. Writing zero to this bit has no effect. Writing a one to this bit resets the entire SPI Interface, including all counters and registers back to their initial state. R/W 0h VCC1_R ESET 3:2 SPDIN_SELECT The SPDIN Select which SPI input signals are enabled when the BIOEN bit is configured as an input. 1xb=SPDIN1 and SPDIN2. Select this option for Dual Mode 01b=SPDIN2 only. Select this option for Half Duplex 00b=SPDIN1 only. Select this option for Full Duplex R/W 0h VCC1_R ESET |
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