MEC1322 datasheet(332/456 Pages) MICROCHIP

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MEC1322

DS00001719D-page 332

 2014 - 2015 Microchip Technology Inc.

28.8.3.1

PWM WDT

When the PWM is configured as a general-purpose PWM (in the Blinking configuration with the 48 MHz clock), the PWM

includes a Watch Dog Timer (WDT). The WDT consists of an internal 8-bit counter and an 8-bit reload value (the field

WDTLD in LED Configuration Register register). The internal counter is loaded with the reset value of WDTLD (14h, or

4 seconds) on system VCC1_RESET and loaded with the contents of WDTLD whenever either the LED Configuration

Register register is written or the MIN byte in the LED Limits Register register is written (the MIN byte controls the duty

cycle of the PWM).

Whenever the internal counter is non-zero, it is decremented by 1 for every tick of the 5 Hz clock. If the counter decre-

ments from 1 to 0, a WDT Terminal Count causes an interrupt to be generated and reset sets the CONTROL bit in the

LED Configuration Register to 3h, which forces the PWM to be full on. No other PWM registers or fields are affected.

If the 5 Hz clock halts, the watchdog timer stops decrementing but retains its value, provided the device continues to be

powered. When the 5 Hz clock restarts, the watchdog counter will continue decrementing where it left off.

Setting the WDTLD bits to 0 disables the PWM WDT. Other sample values for WDTLD are:

01h = 200 ms

02h = 400 ms

03h = 600 ms

04h = 800 ms

…

14h = 4seconds

FFh = 51 seconds

28.9

Implementation

In addition to the registers described in Section 28.10, "EC-Only Registers", the PWM is implemented using a number

of components that are interconnected differently when configured for breathing operation and when configured for

blinking/PWM operation.

28.9.1

BREATHING CONFIGURATION

The PSIZE parameter can configure the PWM to one of three modes: 8-bit, 7-bit and 6-bit. The PERIOD CTR counts

ticks of its input clock. In 8-bit mode, it counts from 0 to 255 (that is, 256 steps), then repeats continuously. In this mode,

a full cycle takes 7.8ms (128Hz). In 7-bit mode it counts from 0 to 127 (128 steps), and a full cycle takes 3.9ms (256Hz).

In 6-bit mode it counts from 0 to 63 (64 steps) and a full cycle takes 1.95ms (512Hz).

The output of the LED circuit is asserted whenever the PERIOD CTR is less than the contents of the DUTY CYCLE

manner. When the LED control is off the internal counters and registers are all reset to 0 (i.e. after a write setting the

RESET bit in the LED Configuration Register Register.) Once enabled, the DUTY CYCLE register is increased by an

amount determined by the LED_STEP register and at a rate determined by the DELAY counter. Once the duty cycle

reaches its maximum value (determined by the field MAX), the duty cycle is held constant for a period determined by

the field HD. Once the hold time is complete, the DUTY CYCLE register is decreased, again by an amount determined

by the LED_STEP register and at a rate determined by the DELAY counter. When the duty cycle then falls at or below

the minimum value (determined by the field MIN), the duty cycle is held constant for a period determined by the field

HD. Once the hold time is complete, the cycle repeats, with the duty cycle oscillating between MIN and MAX.

The rising and falling ramp times as shown in FIGURE 28-3: Clipping Example on page 330 can be either symmetric or

asymmetric depending on the setting of the SYMMETRY bit in the LED Configuration Register Register. In Symmetric

mode the rising and falling ramp rates have mirror symmetry; both rising and falling ramp rates use the same (all) 8

TABLE 28-10: GENERAL PURPOSE PWM MODE CALCULATIONS

Parameter

Unit

Equation

Frequency

(48 MHz Ring Oscillator frequency) / (PRESCALE + 1) / 255

‘H’ Width

Seconds

(1/PERIOD) x (DutyCycle/255)

‘L’ Width

Seconds

(1/PERIOD) x (255 - DutyCycle)

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