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MEC1322 Datasheet(PDF) 380 Page - Microchip Technology |
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MEC1322 Datasheet(HTML) 380 Page - Microchip Technology |
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380 / 456 page ![]() MEC1322 DS00001719D-page 380 2014 - 2015 Microchip Technology Inc. 35.8.3 ETM TRACE ENABLE 35.8.4 JTAG ENABLE 35.8.5 WDT EVENT COUNT Offset 1Ch Bits Description Type Default Reset Event 31:1 Reserved R - - 0 TRACE_EN This bit enables the ARM TRACE debug port (ETM/ITM). The Trace Debug Interface pins are forced to the TRACE functions. 0 = ARM TRACE port disabled 1= ARM TRACE port enabled R/W 0b VCC1_R ESET Offset 20h Bits Description Type Default Reset Event 31:1 Reserved R - - 0JTAG_EN This bit enables the JTAG debug port. 0 = JTAG port disabled. JTAG cannot be enabled (i.e., the TRST# pin is ignored and the JTAG signals remain in their non-JTAG state). 1= JTAG port enabled. A high on TRST# enables JTAG R/W 0b VCC1_R ESET Offset 28h Bits Description Type Default Reset Event 31:4 Reserved R - - 3:0 WDT_COUNT These EC R/W bits are cleared to 0 on VCC1 POR, but not on a WDT. Note: This field is written by Boot ROM firmware to indicate the number of times a WDT fired before loading a good EC code image. R/W 0b VCC1_R ESET |
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