MEC1322 datasheet(405/456 Pages) MICROCHIP

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DS00001719D-page 405

MEC1322

38.7

PECI Interface

Note 38-9

The originator must drive a more restrictive time to allow for quantized sampling errors by a client

yet still attain the minimum time less than 500 µsec. tBIT limits apply equally to tBIT-A and tBIT-M . The

MEC1322 is designed to support 2 MHz, or a 500ns bit time. See the PECI 3.0 specification from

Intel Corp. for further details.

Note 38-10

The minimum and maximum bit times are relative to tBIT defined in the Timing Negotiation pulse. See

the PECI 3.0 specification from Intel Corp. for further details.

Note 38-11

“#nodes” is the number of nodes on the PECI bus; host and client nodes are counted as one each.

Extended trace lengths may appear as extra nodes. Refer also to Table 23-2, "PECI Routing

Guidelines". See the PECI 3.0 specification from Intel Corp. for further details.

Table 1.1

Name

Description

MIN

MAX

Units

Notes

tBIT

Bit time (overall time evident on PECI pin)

Bit time driven by an originator

0.495

500

250

µsec

Note 38-9

tBIT,jitter

Bit time jitter between adjacent bits in a PECI mes-

sage header or data bytes after timing has been

negotiated

tBIT,drift

Change in bit time across a PECI address or PECI

message bits as driven by the originator. This limit

only applies across tBIT-A bit drift and tBIT-M drift.

tH1

High level time for logic 1

0.6

0.8

tBIT

Note 38-

tH0

High level time for logic 0

0.2

0.4

tBIT

tPECIR

Rise time

(measured from VOL to VIH,min , Vtt(nom)−5%)

-30 +

(5 x #nodes)

Note 38-

tPECIF

Fall time

(measured from VOH to VIL,max , Vtt(nom)+5%)

(30 x #nodes)

Note 38-

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