MEC1322 datasheet(408/456 Pages) MICROCHIP

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MEC1322

DS00001719D-page 408

 2014 - 2015 Microchip Technology Inc.

38.10 PS/2 Timing

FIGURE 38-15:

PS/2 TRANSMIT TIMING

TABLE 38-14: PS/2 CHANNEL TRANSMISSION TIMING PARAMETERS

Name

Description

MIN

TYP

MAX

Units

The PS/2 Channel’s CLK and DATA lines

are floated following PS2_EN=1 and

PS2_T/R=0.

1000

PS2_T/R bit set to CLK driven low prepar-

ing the PS/2 Channel for data transmis-

sion.

CLK line floated to XMIT_IDLE bit de-

asserted.

1.7

Trailing edge of WR to Transmit Register to

DATA line driven low.

Trailing edge of EC WR of Transmit Regis-

ter to CLK line floated.

130

Initiation of Start of Transmit cycle by the

PS/2 channel controller to the auxiliary

peripheral’s responding by latching the

Start bit and driving the CLK line low.

0.002

25.003

Period of CLK

302

µs

Duration of CLK high (active)

151

Duration of CLK low (inactive)

t10

Duration of Data Frame. Falling edge of

Start bit CLK (1st clk) to falling edge of Par-

ity bit CLK (10th clk).

2.002

PS2_CLK

PS2_DAT

PS2_EN

PS2_T/R

XMIT_IDLE

RDATA_RDY

Write Tx Reg

Interrupt

t10

t11

t12

t13

t14

t15

Note 1

t17

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