MEC1322 datasheet(410/456 Pages) MICROCHIP

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MEC1322

DS00001719D-page 410

 2014 - 2015 Microchip Technology Inc.

TABLE 38-15: PS/2 CHANNEL RECEIVE TIMING DIAGRAM PARAMETERS

Name

Description

MIN

TYP

MAX

Units

The PS/2 Channel’s CLK and DATA lines

are floated following PS2_EN=1 and

PS2_T/R=0.

1000

Period of CLK

302

µs

Duration of CLK high (active)

151

Duration of CLK low (inactive)

DATA setup time to falling edge of CLK.

MEC1322 samples the data line on the fall-

ing CLK edge.

DATA hold time from falling edge of CLK.

MEC1322 samples the data line on the fall-

ing CLK edge.

Duration of Data Frame. Falling edge of

Start bit CLK (1st clk) to falling edge of Par-

ity bit CLK (10th clk).

2.002

Falling edge of 11th CLK to RDATA_RDY

asserted.

1.6

µs

Trailing edge of the EC’s RD signal of the

Receive Register to RDATA_RDY bit de-

asserted.

500

t10

Trailing edge of the EC’s RD signal of the

Receive Register to the CLK line released

to high-Z.

t11

PS2_CLK is "Low" and PS2_DATA is "Hi-

Z" when PS2_EN is de-asserted.

t12

RDATA_RDY asserted an interrupt is gen-

erated.

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