MEC1322 datasheet(416/456 Pages) MICROCHIP

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MEC1322

DS00001719D-page 416

 2014 - 2015 Microchip Technology Inc.

Note 1:

The BC-Link Master DATA input (tIH in Table 38-21) must be stable before next rising edge of CLK.

The BC-Link Clock frequency is limited by the application usage model (see BC-Link Master Section 31.5,

Signal Description). The BC-Link Clock frequency is controlled by the BC-Link Clock Select Register. The

tc(High Speed) parameter implies both BC-link master and companion devices are located on the same cir-

cuit board and a high speed clock setting is possible.

FIGURE 38-23:

BC-LINK WRITE TIMING

TABLE 38-21: BC-LINK MASTER TIMING DIAGRAM PARAMETERS

Name

Description

MIN

TYP

MAX

Units

tc(High Speed)

High Spec BC Clock Frequency

23.5

24.5

MHz

High Spec BC Clock Period

40.8

41.67

42.5

tOS

BC-Link Master DATA output setup time

before rising edge of CLK.

tc-tOH-

MAX

nsec

tOH

BC-Link Master Data hold time after falling

edge of CLK

nsec

tIS

BC-Link Master DATA input setup time

before rising edge of CLK.

nsec

tIH

BC-Link Master DATA input hold time after

rising edge of CLK.

0nsec

Note:

The timing budget equation is as follows for data from BC-Link slave to master:

Tc > TOD(master-clk) + Tprop(clk) +TOD(slave) + Tprop(slave data) + TIS(master).

Bit n

Bit n-1

tOH

tOS

BC_DAT

BC_CLK

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