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MEC1322 Datasheet(PDF) 418 Page - Microchip Technology |
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MEC1322 Datasheet(HTML) 418 Page - Microchip Technology |
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418 / 456 page ![]() MEC1322 DS00001719D-page 418 2014 - 2015 Microchip Technology Inc. FIGURE 38-25: SPI SETUP AND HOLD TIMES, CLKPOL=0, TCLKPH=0, RCLKPH=0 FIGURE 38-26: SPI SETUP AND HOLD TIMES, CLKPOL=0, TCLKPH=0, RCLKPH=1 38.17.1 SPI INTERFACE TIMINGS The following timing diagrams represent a single-byte transfer over the SPI interface using different SPCLK phase set- tings. Data bits are transmitted in bit order starting with the MSB (LSBF=‘0’) or the LSB (LSBF=‘1’). See the SPI Control Register for information on the LSBF bit. The CS signal in each diagram is a generic bit-controlled chip select signal required by most peripheral devices. This signal and additional chip selects can be GPIO controlled. Note that these timings for Full Duplex Mode are also applicable to Half Duplex (or Bi-directional) mode. TABLE 38-23: SPI SETUP AND HOLD TIMES PARAMETERS NAME DESCRIPTION MIN TYP MAX UNITS T1 Data Output Delay 5 ns T2 Data IN Setup Time 10 ns T3 Data IN Hold Time 0 ns SPDIN SPDOUT T1 T2 T3 SPCLK (CLKPOL = 0, TCLKPH = 0, RCLKPH = 0) Setup and Hold Times for Full-Duplex and Bidrectional Modes SPDIN SPDOUT T1 T2 T3 SPCLK (CLKPOL = 0, TCLKPH = 0, RCLKPH = 1) Setup and Hold Times for Full-Duplex and Bidrectional Modes |
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