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MEC1322 Datasheet(PDF) 422 Page - Microchip Technology |
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MEC1322 Datasheet(HTML) 422 Page - Microchip Technology |
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422 / 456 page  MEC1322 DS00001719D-page 422 2014 - 2015 Microchip Technology Inc. 38.19 JTAG Interface Timing FIGURE 38-32: JTAG POWER-UP & ASYNCHRONOUS RESET TIMING FIGURE 38-33: JTAG SETUP & HOLD PARAMETERS TABLE 38-25: JTAG INTERFACE TIMING PARAMETERS Name Description MIN TYP MAX Units tsu JTAG_RST# de-assertion after VCC1 power is applied 5ms tpw JTAG_RST# assertion pulse width 500 nsec fclk JTAG_CLK frequency (see note) 48 MHz tOD TDO output delay after falling edge of TCLK. 5 10 nsec tOH TDO hold time after falling edge of TCLK 1 TCLK - tOD nsec tIS TDI setup time before rising edge of TCLK. 5 nsec tIH TDI hold time after rising edge of TCLK. 5 nsec Note: fclk is the maximum frequency to access a JTAG Register. VCC1 Power JTAG_RST# tpw fclk tsu 2.8V JTAG_CLK JT A G _C LK JT A G _T D O JT A G _T D I tOD tIH tIS tOH |
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