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MEC1322 Datasheet(PDF) 421 Page - Microchip Technology |
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MEC1322 Datasheet(HTML) 421 Page - Microchip Technology |
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421 / 456 page ![]() 2014 - 2015 Microchip Technology Inc. DS00001719D-page 421 MEC1322 38.18 Serial Debug Port Timing FIGURE 38-31: SERIAL DEBUG PORT TIMING PARAMETERS Note 38-15 When the clock divider for the embedded controller is an odd number value greater than 2h, then tCLK-L = tCLK-H + 15 ns. When the clock divider for the embedded controller is 0h, 1h, or an even number value greater than 2h, then tCLK-L = tCLK-H. TABLE 38-24: SERIAL DEBUG PORT INTERFACE TIMING PARAMETERS Name Description MIN TYP MAX Units fclk TFDP Clock frequency (Note 38-15)6 - 24 MHz tP TFDP Clock Period. 1/fclk μs tOD TFDP Data output delay after falling edge of MSCLK. 5 nsec tOH TFDP Data hold time after falling edge of TFDP Clock tP - tOD nsec tCLK-L TFDP Clock Low Time tP/2 - 3 tP/2 + 3 nsec tCLK-H TFDP Clock high Time (see Note 38-15)tP/2 - 3 tP/2 + 3 nsec tOD tOH tP tCLK-L tCLK-H fCLK TFDP Clock TFDP Data |
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