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DP83867CS Datasheet(PDF) 13 Page - Texas Instruments |
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DP83867CS Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 114 page ![]() SG_RXCK (single ended) SG_RXCK (differential) SG_RXDA (single ended) SG_RXDA (differential) T3 (min) tT1t tT2t T3 (max) DP83867CS, DP83867IS, DP83867E www.ti.com SNLS504 – OCTOBER 2015 8.9 SGMII Timing (1) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT T1 SGMII Clock Output Duty Cycle 48 52 % T2 Setup time See (2) 100 ps T3 Clock to Data relationship from See (3) either edges of the clock to valid 250 550 ps data TR VOD fall time 20% - 80% 100 200 ps TF VOD rise time 20% - 80% 100 200 ps Thold Hold time See (2) 100 ps (1) Ensured by production test, characterization, or design. (2) Setup and hold time are measured at 50% of the transition. (3) T3 is measured at 0 V differential. Figure 4. SGMII Timing Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 13 |
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