TLF9461

December 1994

54F74F14

Hex Inverter Schmitt Trigger

General Description

The ’F14 contains six logic inverters which accept standard

TTL input signals and provide standard TTL output levels

They are capable of transforming slowly changing input sig-

nals into sharply defined jitter-free output signals In addi-

tion they have a greater noise margin than conventional

inverters

Each circuit contains a Schmitt trigger followed by a Darling-

ton level shifter and a phase splitter driving a TTL totem-

pole output The Schmitt trigger uses positive feed back to

effectively speed-up slow input transition and provide differ-

ent input threshold voltages for positive and negative-going

transitions This hysteresis between the positive-going and

negative-going input thresholds (typically 800 mV) is deter-

mined internally by resistor ratios and is essentially insensi-

tive to temperature and supply voltage variations

Features

Y

Guaranteed 4000V minimum ESD protection

Y

Standard Military Drawing

5962-88752

Commercial

Military

Package

Package Description

Number

74F14PC

N14A

14-Lead (0300 Wide) Molded Dual-In-Line

54F14DM (Note 2)

J14A

14-Lead Ceramic Dual-In-Line

74F14SC (Note 1)

M14A

14-Lead (0150 Wide) Molded Small Outline JEDEC

74F14SJ (Note 1)

M14D

14-Lead (0300 Wide) Molded Small Outline EIAJ

54F14FM (Note 2)

W14B

14-Lead Cerpack

54F14LM (Note 2)

E20A

20-Lead Ceramic Leadless Chip Carrier Type C

Note 1

Devices also available in 13

Note 2

Logic Symbol

IEEEIEC

TLF9461 – 3

Connection Diagrams

Pin Assignment

DIP SOIC and Flatpak

TLF9461 – 1

Pin Assignment

for LCC

TLF9461 – 2

TRI-STATE

is a registered trademark of National Semiconductor Corporation

C1995 National Semiconductor Corporation

RRD-B30M75Printed in U S A