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TPD2S017DBVR Datasheet(PDF) 9 Page - Texas Instruments |
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TPD2S017DBVR Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 16 page ![]() Ch2_In GND Vcc Ch1_In Ch2_In Ch2_Out Ch1_Out Ch2_Out Ch1_Out Ch1_Out Power Ground LEGEND VIA to Power Ground Plane VIA to Power Supply Plane TPD2S017 www.ti.com SLLS949B – SEPTEMBER 2009 – REVISED DECEMBER 2015 9 Power Supply Recommendations The optional VCC power supply bias is recommended to lower the I/O capacitances. Ensure that the maximum voltage specifications for each pin are not violated. 10 Layout 10.1 Layout Guidelines • The optimum placement is as close to the connector as possible. – EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures. – The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector. • Route the protected traces as straight as possible. • Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded corners with the largest radii possible. – Electric fields tend to build up on corners, increasing EMI coupling. • Use thick and short traces for the power and ground paths. • Run differential signal lines in pair with small distance to optimize signal integrity. 10.2 Layout Example Figure 9. Layout Recommendation Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: TPD2S017 |
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