TUSB4041IPAP datasheet(13/44 Pages) TI1

13 / 44 page

24 MHz

CL2

10 M

CL1

TUSB4041I

www.ti.com

SLLSEK3B – JULY 2015 – REVISED DECEMBER 2015

Table 2. OTP Configurable Features (continued)

CONFIGURATION REGISTER

BIT FIELD

DESCRIPTION

OFFSET

Port-removable configuration for downstream ports 2. OTP configuration is

REG_07h

[1]

inverse of rmbl[3:0], that is 1 = not removable, 0 = removable.

Port-removable configuration for downstream ports 3. OTP configuration is

REG_07h

[2]

inverse of rmbl[3:0], that is 1 = not removable, 0 = removable.

Port-removable configuration for downstream ports 4. OTP configuration is

REG_07h

[3]

inverse of rmbl[3:0], that is 1 = not removable, 0 = removable.

REG_0Ah

[3]

Enable device attach detection

REG_0Ah

[4]

High-current divider mode enable

REG_0Bh

[0]

USB 2.0 port polarity configuration for downstream ports 1

REG_0Bh

[1]

USB 2.0 port polarity configuration for downstream ports 2

REG_0Bh

[2]

USB 2.0 port polarity configuration for downstream ports 3

REG_0Bh

[3]

USB 2.0 port polarity configuration for downstream ports 4

REG_F0h

[3:1]

USB power switch power-on delay

8.3.4 Clock Generation

The TUSB4041I device accepts a crystal input to drive an internal oscillator or an external clock source. If a clock

is provided to the XI pin instead of a crystal, the XO pin is left open. Otherwise, if a crystal is used, the

connection must follow these guidelines. Because the XI and XO pins are coupled to other leads and supplies on

the PCB, keep traces as short as possible and away from any switching leads. Minimize the capacitance

between the XI and XO pins by shielding C1 and C2 with the clean ground lines.

Figure 2. TUSB4041I Clock

8.3.5 Crystal Requirements

The crystal must be fundamental mode with load capacitance of 12 to 24 pF and frequency stability rating of

±100 PPM or better. To ensure proper startup oscillation condition, TI recommends a maximum crystal

equivalent series resistance (ESR) of 50

Ω. If a crystal source is used, use a parallel load capacitor. The exact

load capacitance value used depends on the crystal vendor. Refer to application note Selection and Specification

for Crystals for Texas Instruments USB 2.0 Devices (SLLA122) for details on how to determine the load

capacitance value.

8.3.6 Input Clock Requirements

When using an external clock source such as an oscillator, the reference clock should have a frequency stability

of ±100 PPM or better and have less than 50-ps absolute peak-to-peak jitter. Tie XI to the 1.8-V clock source,

and leave XO floating.

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