TLF9523

May 1995

54F74F373

Octal Transparent Latch with TRI-STATE

Outputs

General Description

The ’F373 consists of eight latches with TRI-STATE outputs

for bus organized system applications The flip-flops appear

transparent to the data when Latch Enable (LE) is HIGH

When LE is LOW the data that meets the setup times is

latched Data appears on the bus when the Output Enable

(OE) is LOW When OE is HIGH the bus output is in the high

impedance state

Features

Y

Eight latches in a single package

Y

TRI-STATE outputs for bus interfacing

Y

Guaranteed 4000V minimum ESD protection

Commercial

Military

Package

Package Description

Number

74F373PC

N20A

20-Lead (0300 Wide) Molded Dual-In-Line

54F373DM (QB)

J20A

20-Lead Ceramic Dual-In-Line

74F373SC (Note 1)

M20B

20-Lead (0300 Wide) Molded Small Outline JEDEC

74F373SJ (Note 1)

M20D

20-Lead (0300 Wide) Molded Small Outline EIAJ

74F373MSA (Note 1)

MSA20

20-Lead Molded Shrink Small Outline EIAJ Type II

54F373FM (QB)

W20A

20-Lead Cerpack

54F373LM (QB)

E20A

20-Lead Ceramic Leadless Chip Carrier Type C

Note 1

Devices also available in 13

Logic Symbols

Connection Diagrams

IEEEIEC

TLF9523 – 4

TLF9523 – 1

Pin Assignment

for DIP SOIC SSOP and Flatpak

TLF9523 – 2

Pin Assignment

for LCC

TLF9523 – 3

TRI-STATE

is a registered trademark of National Semiconductor Corporation

C1995 National Semiconductor Corporation

RRD-B30M75Printed in U S A