RF430CL331HIPWR datasheet(25/60 Pages) TI1

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Data Requested

1. PCD ± ReadBinary Request

(interrupt):

More data supplied than required - caching

2. Host ± Service Request

Sent

3. PICC ± Next Request (no interrupt):

Automatically Sending

Sent

4. PICC ± Next Request (insufficient data):

Sent

Cached

Have

Need

Buffer shifted internally

(then interrupt)

Request Parameters:

buffer_start_index = L

length_requested = N - L

Entire Buffer Space (not to scale)

6. Next Request: Cycle repeats

5. Host ± Service Request:

Sending

RF430CL331H

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SLASE18A – SEPTEMBER 2015 – REVISED NOVEMBER 2015

In normal read mode, when Read Prefetch functionality has not been enabled, each Read Binary request

that comes in, is passed to the host controller and the internal state machine is in blocking mode until the

data is sent back to the RF430CL331H . The RF430CL331H uses the same memory for each request, it is

no more than the size of the read request packet length.

5.9.2.2

NDEF Read Command Internal Buffer Handling (With Caching)

Figure 5-10. Read Buffer Flow (with caching)

1. PCD requests a block of data. PICC received the requests, sets up the internal register and asserts the

INTO interrupt.

2. Host controller supplies the request but also adds more data on the file that is continuous with this

request.

3. The next PCD request is fulfilled automatically because the data that is requested is already in the

buffer. The host controller is not interrupted.

4. The next PCD request has insufficient data, so the data that is available is shifted to the beginning of

the buffer and the unavailable data is requested.

5. The full request is transmitted out.

6. The cycle can repeat.

Detailed Description

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