2

SCD5900 Rev G 4/8/13

Aeroflex Plainview

16-Pin SOIC

OUT_A

-IN_A

+IN_A

VCC

+IN_B

-IN_B

OUT_B

N/C

OUT_D

-IN_D

+IN_D

VEE

+IN_C

-IN_C

OUT_C

N/C

RHD5900

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

Notes:

1. Package and lid are electrically isolated from signal pads.

2. It is recommended that N/C or no connect pins (pins 8 and 9) and lid be grounded. This eliminates or minimizes any ESD or static buildup.

OUT_B

OUT_A

OUT_C

OUT_D

3

2

5

6

12

11

14

15

16

10

7

1

+IN_A

-IN_A

+IN_B

-IN_B

+IN_C

-IN_C

+IN_D

-IN_D

A

B

C

D

4

13

VCC

VEE

FIGURE 2: PACKAGE PIN-OUT

FIGURE 1: BLOCK DIAGRAM