2

SCD5940 Rev A Advanced 1/10/12

Aeroflex Plainview

FIGURE 1: BLOCK DIAGRAM

The analog input impedance is primary capacitance (20pF). The input voltage charges a track-and-hold hold

capacitor through transmission gates. The input bandwidth is determined by the slew rate of the hold amplifier

and is adequate to allow input sampling in three clock periods (3uS nominal). The ultimate bandwidth is

determined by the aperture uncertainty associated with the closing of the sample gate (approximately 5nS). The

converter bandwidth is then determined by the sampling Nyquist frequency rather than the input signal; change

rate (dv/dt) and the LSB weight in volts as would be the case if there were no sample and hold.

Start-Convert (STCNV_H), Busy (BUSY_L) and End-Of-Convert (EOC_H) status and control line are provided.

The converter will operate in either continuous or single conversion modes. The digital output register changes at

the end of a conversion and is available until the next End-Of-Convert. Digital input and output circuits operate

from a voltage independent of the remainder of the chip such that I/O is compatible with digital systems from less

than 3.3 to 5 volts.

The converter divides the reference voltage into 16 segments with a linear weighted resistor network. The voltage

on any segment is passed to a linear 10-bit DAC for interpolation. The architecture is inherently capable of

monotonic operation. INL is ±10 LSBs. DNL is ±1/2 LSB. The sampled input voltage is compared to the output

of the two stage DAC for a 14-bit successive approximation conversion.

All inputs are protected to both power supply rails by semiconductor diodes. Inputs should be constrained to Vcc

+0.4 and Vee-0.4 to avoid forward biasing protection paths.

application dependant.