Data Sheet TLE 6230 GP

V2.1

Page

26. Aug. 2002

7

Functional Description

The TLE 6230 GP is an octal-low-side power switch which provides a serial peripheral inter-

face (SPI) to control the 8 power DMOS switches, as well as diagnostic feedback. The power

voltage by an active zener clamp.

The diagnostic logic recognizes a fault condition which can be read out via the serial diagnos-

tic output (SO).

Circuit Description

Output Stage Control

Each output is independently controlled by an output latch and a common reset line, which

disables all eight outputs. Serial data input (SI) is read on the falling edge of the serial clock. A

logic high input data bit turns the respective output channel ON, a logic low data bit turns it

Special conditions for Channel 1 to 4:

In addition to the serial control of the outputs it is possible to control channel 1 to channel 4

directly in parallel for PWM applications. These inputs are high or low active (programmable

via PRG pin) and ANDed with the SPI control bit.

The table shows the AND-operation of the parallel

input pin (here active high) and the corresponding

SPI bit. For an application where the parallel input is

always "ON", it is possible to switch the channel

OFF via the SPI bit, e.g. for diagnosis in OFF-state.

SPI Priority for OFF-state

Operation with parallel inputs: Set SPI bits to logic high.

Operation via SPI: Connect parallel inputs to logic high (if programmed to active high).

PRG - Program pin.

PRG = Low (GND): Parallel inputs Channel 1 to 4 are low active.

If the parallel input pins are not connected (independent of high or low activity) it is guaranteed

that the channels 1 to 4 are switched OFF.

PRG pin itself is internally pulled up when it is not connected.

IN 1 - 4

SPI-Bit 0 - 3

OUT 1 - 4

00

OFF

01

OFF

10

OFF

11

ON