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UT54ACTS165 Datasheet(PDF) 1 Page - Aeroflex Circuit Technology |
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UT54ACTS165 Datasheet(HTML) 1 Page - Aeroflex Circuit Technology |
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1 / 10 page ![]() 1 Standard Products UT54ACS165/UT54ACTS165 8-Bit Parallel Shift Registers Datasheet November 2010 www.aeroflex.com/logic FEATURES Complementary outputs Direct overriding load (data) inputs Gated clock inputs Parallel-to-serial data conversions 1.2μ CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 16-pin DIP - 16-lead flatpack UT54ACS165 - SMD 5962-96558 UT54ACTS165 - SMD 5962-96559 DESCRIPTION The UT54ACS165 and the UT54ACTS165 are 8-bit serial shift regis- ters that, when clocked, shift the data toward serial output QH. Parallel- in access to each stage is provided by eight individual data inputs that are enabled by a low level at the SH/LD input. The devices feature a clock inhibit function and a complemented serial output QH . Clocking is accomplished by a low-to-high transition of the CLK input while SH/LD is held high and CLK INH is held low. The functions of the CLK and CLK INH (clock inhibit) inputs are interchangeable. Since a low CLK input and a low-to-high transition of CLK INH will also accomplish clocking, CLK INH should be changed to the high level only while the CLK input is high. Parallel loading is disabled when SH/LD is held high. Parallel inputs to the registers are enabled while SH/LD is low independently of the levels of CLK, CLK INH or SER inputs. The devices are characterized over full military temperature range of -55 °C to +125°C. FUNCTION TABLE Note: 1. Qn = The state of the referenced output one setup time prior to the Low-to- High clock transition.PINOUTS PINOUTS 16-Pin DIP Top View 16-Lead Flatpack Top View LOGIC SYMBOL INPUTS INTERNAL OUTPUTS OUTPUTS SH/ LD CLK INH CLK SER PARALLEL A . . . H QA QB QH QH L X X X a . . . h a b h h H L L X X QA QB QH QH H L ↑ H X H QA QG QG H L ↑ L X L QA QG QG H H X X X QA QB QH QH 1 2 3 4 5 7 6 16 15 14 13 12 10 11 SH/LD CLK E F G H QH VDD CLK INH D C B A SER 8 9 VSS QH 1 2 3 4 5 7 6 16 15 14 13 12 10 11 VDD 89 SH/LD CLK E F G H QH CLK INH D C B A SER VSS QH (1) SH/LD (15) CLK INH C2/ C1 (LOAD) Note: 1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. (10) SER (11) A SRG8 (9) QH (7) QH ≥1 (2) CLK 2D 1D (12) B (13) C (14) D (3) E (4) F (5) G (6) H 1D 1D |
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