VRG8691 datasheet(6/10 Pages) AEROFLEX

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SCD8691 Rev H 11/12/13

Aeroflex Plainview

VRG8691/92

VIN

VOUT

VSENSE

CURR. LIMIT

ENABLE

0.1µF

47µF

VBIAS

SLOW START

VBIAS

VIN

GND

0.1µF

CDELAY

FIGURE 5 – DELAYED ENABLE

APPLICATION NOTE 3

START UP SEQUENCE

Recommended Power Supply Sequencing Options:

- OPTION 1: Controlling the ENABLE line with a Digital signal (TTL / CMOS compatible).

- Prior to applying power, disable the regulator by setting the ENABLE control line to a HIGH state.

- Apply VIN and VBIAS. 1/

- Wait until both VIN and VBIAS supplies have reached their operating levels.

- Toggle the ENABLE control line to a LOW state to turn on VOUT of the regulator.

- OPTION 2: Controlling the ENABLE line using the CDELAY feature.

- Connect a CDELAY capacitor between VBIAS and the ENABLE as shown in Figure 5 below. 2/

- Apply VIN and VBIAS. 1/

- CDELAY causes the regulator to self-enable after VBIAS has reached operating level.

NOTE: The ENABLE should always be asserted AFTER VIN and VBIAS have reached operating level.

NOTES:

1/ VIN should be applied before VBIAS if the Slow Start feature is used.

2/ CDELAY capacitor of 10uF is adequate for VBIAS rise times of up to 50ms.

VREF (=1V)

IADJ

CLOAD

47µF

VOUT

TANT

1µF

TANT

CER

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