UT04VS33P datasheet(11/21 Pages) AEROFLEX

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sistive divider, the maximum voltage of the monitored signal

can be greater than the maximum level when using the preset

threshold, as given by:

Vmonitor < [(RT + RB)/RB] * VRFTH

where RT is the top resistor of the divider and RB is the lower

resistor, tied to VSS. One should account for resistor toleranc-

es. Also, with the resistive divider tied to VSS, the minimum

voltage that can be monitored is VRFTH. It is possible to tie the

resistive divider to the VDD supply and, hence, monitor signals

lower than VRFTH. If this arrangement is used, the variation in

the VDD supply will affect the result.

Enables

Each channel has an enable, ENx. When a channel is disabled

its corresponding output is held in the logic 0 state. Also, the

outputs are not affected by any changes of signals that may oc-

cur on disabled channels. However, when a channel is enabled,

the outputs are put into the mode for the length of time as deter-

mined by RESET timeout. As noted, when the OVSH is logic

1, the enables of channels 1 and 3 are connected together to af-

fect channel 1 output and those for channels 2 and 4 affect chan-

nel 2 output. See Figure 4 for timing. The condition whereby all

four enables are in the logic 0 state is reserved and should not

be used.

Master Reset

The device has a master reset (inverted logic) input, MRB,

which provides a means for the system reset to be combined

with the voltage supervisor reset functionality. The timing of

this input with respect to the RESET/RESETB outputs is shown

in Figure 5. Timing specifications are given in the AC Charac-

teristics table. An RC time constant can be associated with this

pin to extend the RESET state.

Timing (CDLY, CRESET)

Many of the timing parameters of the device are fixed and listed

in the AC Characteristics table. Along with those are the default

value for the CDLY function, response time of VOUTx after

the corresponding input signal becomes valid, and the C func-

tion, defining the timeout until an output is released after an

event (an ENx or all enabled VOUTx becoming valid).

CDLY timing

The delay time (tDELAY+) for each channel is independently ad-

justable by adding a capacitor to the desired CDLYx pin. The

equation that defines the delay is:

tDELAY+ = (Cdly + 18pF) * (VTH_CDLY)/ ICH_CDLY

where Cdly is the user chosen, external capacitance connected

to CDLY pin, 18pF is the internal capacitance (any significant

board capacitance should be added), ICH_CDLY is the charging

current with value given in the DC Characteristics table and

VTH_CDLY is the threshold voltage utilized by this function,

also given in the DC Characteristics table.

CRESET timing

The timeout for the outputs (tRP) when activated by changes of

an ENx or VINx signal, is adjustable by the addition of an ex-

ternal capacitor to the CRESET pin. The equation that defines

the RESET timeout period is:

tRP=(Creset+ 40pF)*(VTH_CRESET) /ICH_RESET

where Creset is the user chosen, external capacitance, 40pF is

the device default and parasitic capacitance (any significant

board capacitance should be added), ICH_RESET is the charging

current with value given in the DC Characteristics table and

VTH_CRESET is the threshold voltage utilized by this function,

also given in the DC Characteristics table.

Output drive (open drain - power, speed)

The outputs from the device, RESET, RESETB and VOUTx

are of the open drain type, having only an active pulldown, with

characteristics given in the DC and AC Characteristics tables.

Hence, the user must supply an appropriate valued resistor for

the pullup. Note: This allows for 1) the connecting of several

outputs from the given device or other devices and 2) provides

for voltage drive-level adjustment by connecting the resistor to

an appropriate supply (note the voltage level is constrained by

the operating voltage of this device, VDD).

INV function

For further system interface flexibility, the INV pin provides

for the logical inversion of the channel 3 and 4 VOUT signals.

In all modes, the logic level of the output is inverted from its

normal state.

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