Truth Table

Mode Select-Function Table

Operating Mode

Inputs

Output

MR

CP

D

n

Q

n

Reset (Clear)

L

X

X

L

Load “1”

H

N

h

H

Load “0”

H

N

l

L

H = HIGH Voltage Level steady state

h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock tran-

sition

L = LOW Voltage Level steady state

I = LOW Voltage Level one setup time prior to the LOW-to-HIGH clock tran-

sition

X = Immaterial

N = LOW-to-HIGH clock transition

Logic Diagram

DS100956-3

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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